Invention Grant
- Patent Title: Self aligned gate shape preventing void formation
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Application No.: US15471733Application Date: 2017-03-28
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Publication No.: US09773885B2Publication Date: 2017-09-26
- Inventor: Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
- Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION , GLOBALFOUNDRIES Inc. , STMicroelectronics, Inc.
- Applicant Address: US NY Armonk KY Grand Cayman US TX Coppell
- Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,GLOBALFOUNDRIES INC.,STMICROELECTRONICS, INC.
- Current Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION,GLOBALFOUNDRIES INC.,STMICROELECTRONICS, INC.
- Current Assignee Address: US NY Armonk KY Grand Cayman US TX Coppell
- Agency: Tuntunjian & Bitetto, P.C.
- Agent Vazken Alexanian
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L29/66 ; H01L21/762 ; H01L29/78 ; H01L29/06 ; H01L21/306

Abstract:
A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
Public/Granted literature
- US20170200807A1 SELF ALIGNED GATE SHAPE PREVENTING VOID FORMATION Public/Granted day:2017-07-13
Information query
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