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公开(公告)号：US20170200807A1
公开(公告)日：2017-07-13
申请号：US15471733
申请日：2017-03-28
发明人： Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/66 , H01L21/306 , H01L29/06 , H01L21/762 , H01L29/78
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66515 , H01L29/66795 , H01L29/785
摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
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公开(公告)号：US20170178967A1
公开(公告)日：2017-06-22
申请号：US15359953
申请日：2016-11-23
发明人： Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/8234 , H01L29/66 , H01L29/49 , H01L27/088
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66515 , H01L29/66795 , H01L29/785
摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
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公开(公告)号：US09773885B2
公开(公告)日：2017-09-26
申请号：US15471733
申请日：2017-03-28
发明人： Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L21/336 , H01L29/66 , H01L21/762 , H01L29/78 , H01L29/06 , H01L21/306
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66515 , H01L29/66795 , H01L29/785
摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
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公开(公告)号：US09640633B1
公开(公告)日：2017-05-02
申请号：US14974589
申请日：2015-12-18
发明人： Andrew M. Greene , Qing Liu , Ruilong Xie , Chun-Chen Yeh
IPC分类号： H01L29/66 , H01L29/78 , H01L21/02 , H01L21/306
CPC分类号： H01L29/66545 , H01L21/76224 , H01L21/823418 , H01L21/823431 , H01L21/823468 , H01L21/823475 , H01L21/823481 , H01L27/0886 , H01L29/0649 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/66515 , H01L29/66795 , H01L29/785
摘要： A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.
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公开(公告)号：US10818773B2
公开(公告)日：2020-10-27
申请号：US15276060
申请日：2016-09-26
IPC分类号： H01L21/768 , H01L29/66 , H01L21/283 , H01L27/088 , H01L29/417 , H01L23/485 , H01L29/78 , H01L23/532 , H01L23/535 , H01L21/306 , H01L21/8234 , H01L29/08
摘要： A method for forming self-aligned contacts includes patterning a mask between fin regions of a semiconductor device, etching a cut region through a first dielectric layer between the fin regions down to a substrate and filling the cut region with a first material, which is selectively etchable relative to the first dielectric layer. The first dielectric layer is isotropically etched to reveal source and drain regions in the fin regions to form trenches in the first material where the source and drain regions are accessible. The isotropic etching is super selective to remove the first dielectric layer relative to the first material and relative to gate structures disposed between the source and drain regions. Metal is deposited in the trenches to form silicide contacts to the source and drain regions.
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公开(公告)号：US10325848B2
公开(公告)日：2019-06-18
申请号：US16127645
申请日：2018-09-11
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V. V. S. Surisetty , Ruilong Xie
IPC分类号： H01L29/49 , H01L23/528 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/306 , H01L21/3205 , H01L21/283 , H01L21/3213 , H01L21/8234 , H01L29/417 , H01L27/088
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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公开(公告)号：US10236253B2
公开(公告)日：2019-03-19
申请号：US15484309
申请日：2017-04-11
发明人： Andrew M. Greene , Injo Ok , Balasubramanian Pranatharthiharan , Charan V. V. S. Surisetty , Ruilong Xie
IPC分类号： H01L27/088 , H01L23/528 , H01L29/78 , H01L29/66 , H01L21/768 , H01L21/306 , H01L21/3205 , H01L21/283 , H01L21/3213 , H01L29/49 , H01L21/8234 , H01L29/417
摘要： A self-aligned interconnect structure includes a fin structure patterned in a substrate; an epitaxial contact disposed over the fin structure; a first metal gate and a second metal gate disposed over and substantially perpendicular to the epitaxial contact, the first metal gate and the second metal gate being substantially parallel to one another; and a metal contact on and in contact with the substrate in a region between the first and second metal gates.
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公开(公告)号：US20180323110A1
公开(公告)日：2018-11-08
申请号：US16038426
申请日：2018-07-18
IPC分类号： H01L21/8234 , H01L29/66 , H01L21/768 , H01L21/311 , H01L21/02 , H01L27/088 , H01L29/417 , H01L21/3213
CPC分类号： H01L21/823475 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31111 , H01L21/32139 , H01L21/76802 , H01L21/76837 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66636 , H01L29/66795
摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
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公开(公告)号：US09929057B2
公开(公告)日：2018-03-27
申请号：US15342801
申请日：2016-11-03
IPC分类号： H01L21/8234 , H01L21/768 , H01L27/088 , H01L29/66 , H01L21/02 , H01L21/311
CPC分类号： H01L21/823475 , H01L21/02167 , H01L21/0217 , H01L21/02274 , H01L21/31111 , H01L21/32139 , H01L21/76802 , H01L21/76837 , H01L21/823418 , H01L21/823425 , H01L21/823431 , H01L21/823437 , H01L27/088 , H01L29/41783 , H01L29/6653 , H01L29/66545 , H01L29/66553 , H01L29/6656 , H01L29/66636 , H01L29/66795
摘要： A method for filling gaps between structures includes forming a plurality of high aspect ratio structures adjacent to one another with gaps, forming a first dielectric layer on tops of the structures and conformally depositing a spacer dielectric layer over the structures. The spacer dielectric layer is removed from horizontal surfaces and a protection layer is conformally deposited over the structures. The gaps are filled with a flowable dielectric, which is recessed to a height along sidewalls of the structures by a selective etch process such that the protection layer protects the spacer dielectric layer on sidewalls of the structures. The first dielectric layer and the spacer dielectric layer are exposed above the height using a higher etch resistance than the protection layer to maintain dimensions of the spacer layer dielectric through the etching processes. The gaps are filled by a high density plasma fill.
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公开(公告)号：US09837276B2
公开(公告)日：2017-12-05
申请号：US15156651
申请日：2016-05-17
发明人： Andrew M. Greene , Ryan O. Jung , Ruilong Xie
IPC分类号： H01L21/336 , H01L21/283 , H01L21/311 , H01L21/28 , H01L27/02 , H01L29/66
CPC分类号： H01L21/283 , H01L21/0332 , H01L21/28017 , H01L21/31053 , H01L21/31111 , H01L21/31144 , H01L27/0207 , H01L29/6653 , H01L29/66545 , H01L29/66553
摘要： A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
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