Invention Grant
- Patent Title: Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects
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Application No.: US14911991Application Date: 2013-09-27
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Publication No.: US09793159B2Publication Date: 2017-10-17
- Inventor: Charles H. Wallace , Paul A. Nyhus , Elliot N. Tan , Swaminathan Sivakumar
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe Williamson & Wyatt P.C.
- International Application: PCT/YS2013/062327 WO 20130927
- International Announcement: WO2015/047321 WO 20150402
- Main IPC: H01L21/768
- IPC: H01L21/768 ; H01L23/528 ; H01L23/522 ; H01L23/532

Abstract:
Previous layer self-aligned via and plug patterning for back end of line (BEOL) interconnects are described. In an example, an interconnect structure for an integrated circuit includes a first layer disposed above a substrate. The first layer of the interconnect structure includes a grating of alternating metal lines and dielectric lines in a first direction. A second layer of the interconnect structure is disposed above the first layer. The second layer includes a grating of alternating metal lines and dielectric lines in a second direction, perpendicular to the first direction. Each metal line of the grating of the second layer is disposed on a recessed dielectric line composed of alternating distinct regions of a first dielectric material and a second dielectric material corresponding to the alternating metal lines and dielectric lines of the first layer of the interconnect structure.
Public/Granted literature
- US20160190009A1 Previous Layer Self-Aligned Via and Plug Patterning for Back End of Line (BEOL)Interconnects Public/Granted day:2016-06-30
Information query
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