Invention Grant
- Patent Title: High voltage lateral DMOS transistor with optimized source-side blocking capability
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Application No.: US15013334Application Date: 2016-02-02
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Publication No.: US09793375B2Publication Date: 2017-10-17
- Inventor: Philip Leland Hower , Sameer Pendharkar , Marie Denison
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Tuenlap D. Chan; Charles A. Brill; Frank D. Cimino
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L21/336 ; H01L29/78 ; H01L29/08 ; H01L29/10 ; H01L29/06 ; H01L21/266 ; H01L27/088 ; H01L21/225
Abstract:
An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
Public/Granted literature
- US20160163828A1 High Voltage Lateral DMOS Transistor with Optimized Source-Side Blocking Capability Public/Granted day:2016-06-09
Information query
IPC分类:
