Invention Grant
- Patent Title: Data on clock lane of source synchronous links
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Application No.: US14788721Application Date: 2015-06-30
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Publication No.: US09794054B2Publication Date: 2017-10-17
- Inventor: Tapas Nandy , Nitin Gupta
- Applicant: STMicroelectronics International N.V.
- Applicant Address: NL Schiphol
- Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee: STMICROELECTRONICS INTERNATIONAL N.V.
- Current Assignee Address: NL Schiphol
- Agency: Seed Intellectual Property Law Group LLP
- Main IPC: H04L7/00
- IPC: H04L7/00 ; H04L5/00 ; H04J3/06 ; H04L7/033 ; H04L1/00 ; H04L7/027 ; G06F1/10 ; H04L7/02

Abstract:
A source synchronous data transmission system includes a data transmitting device and a data receiving device. A dedicated data line carries a data signal from the data transmission device to the data receiving device. A dedicated clock line carries a modulated clock signal from the data transmission device to the data receiving device. The data transmission device includes a clock data driver configured to encode data into the modulated clock signal by modulating an amplitude of the modulated clock signal. Thus, the clock line of the source synchronous data transmission system carries the clock signal and additional data.
Public/Granted literature
- US20170005780A1 DATA ON CLOCK LANE OF SOURCE SYNCHRONOUS LINKS Public/Granted day:2017-01-05
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