Invention Grant
- Patent Title: Clock generation circuit and semiconductor device provided therewith
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Application No.: US14797825Application Date: 2015-07-13
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Publication No.: US09819352B2Publication Date: 2017-11-14
- Inventor: Takeshi Osada
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Kanagawa-ken
- Agency: Robinson Intellectual Property Law Office
- Agent Eric J. Robinson
- Priority: JP2005-158220 20050530
- Main IPC: H03L7/06
- IPC: H03L7/06 ; H03L7/099 ; H03L7/18

Abstract:
It is an object of the present invention to solve a problem that malfunction of communication is generated by varying a frequency of a clock due to noise from outside in a case where there is no supplied signal in a circuit which performs negative feedback control so that the supplied signal and the feedback signal can maintain a fixed phase relationship between the signals. The present invention provides a configuration including a PLL circuit and an oscillator circuit, where a switch for switching an output between a signal from the PLL circuit and a signal from the oscillator circuit to the signal output portion is provided to switch from a connection to the PLL circuit to a connection to the oscillator circuit in a case where there is no received signal.
Public/Granted literature
- US20150326234A1 CLOCK GENERATION CIRCUIT AND SEMICONDUCTOR DEVICE PROVIDED THEREWITH Public/Granted day:2015-11-12
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