Invention Grant
- Patent Title: Semiconductor device and method of forming stepped interconnect layer for stacked semiconductor die
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Application No.: US14612075Application Date: 2015-02-02
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Publication No.: US09824975B2Publication Date: 2017-11-21
- Inventor: Reza A. Pagaila , Byung Tai Do , Linda Pei Ee Chua
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L23/538
- IPC: H01L23/538 ; H01L25/07 ; H01L21/768 ; H01L25/00 ; H01L21/56 ; H01L23/31 ; H01L23/00 ; H01L25/03 ; H01L25/065

Abstract:
A semiconductor device comprises a first semiconductor die. An encapsulant is disposed around the first semiconductor die. A first stepped interconnect structure is disposed over a first surface of the encapsulant. An opening is formed in the first stepped interconnect structure. The opening in the first stepped interconnect structure is over the first semiconductor die. A second semiconductor die is disposed in the opening of the first stepped interconnect structure. A second stepped interconnect structure is disposed over the first stepped interconnect structure. A conductive pillar is formed through the encapsulant.
Public/Granted literature
- US20150145128A1 Semiconductor Device and Method of Forming Stepped Interconnect Layer for Stacked Semiconductor Die Public/Granted day:2015-05-28
Information query
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