A subsystem configured to implement an analog to digital converter that includes a high speed comparator with an embedded reference voltage level that functions as a calibrated threshold. A calibration element applies power to a reference voltage system. The calibration element then selects a differential analog voltage and applies the differential analog voltage to the inputs of the comparator. A digitally coded signal then configures an array of switches that connect complements of integrated resistors to each input of the comparator so that the switching point of the comparator occurs coincident with the applied differential analog reference voltage, nulling out the effect of the applied differential analog voltage and comparator errors. The calibration element then removes power from the reference voltage system. As a result, the comparator is configured with an embedded threshold that equals the differential analog reference voltage.