Invention Grant
- Patent Title: SPDIF clock and data recovery with sample rate converter
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Application No.: US15484408Application Date: 2017-04-11
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Publication No.: US09832012B2Publication Date: 2017-11-28
- Inventor: Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
- Applicant: AVNERA CORPORATION
- Applicant Address: US OR Beaverton
- Assignee: AVNERA CORPORATION
- Current Assignee: AVNERA CORPORATION
- Current Assignee Address: US OR Beaverton
- Agent Marger Johnson
- Main IPC: H04L7/033
- IPC: H04L7/033 ; H04L7/00

Abstract:
A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.
Public/Granted literature
- US20170222793A1 SPDIF CLOCK AND DATA RECOVERY WITH SAMPLE RATE CONVERTER Public/Granted day:2017-08-03
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