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公开(公告)号：US10476659B2
公开(公告)日：2019-11-12
申请号：US16049474
申请日：2018-07-30
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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公开(公告)号：US20180054297A1
公开(公告)日：2018-02-22
申请号：US15799473
申请日：2017-10-31
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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公开(公告)号：US10038548B2
公开(公告)日：2018-07-31
申请号：US15799473
申请日：2017-10-31
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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公开(公告)号：US08848849B1
公开(公告)日：2014-09-30
申请号：US13800557
申请日：2013-03-13
Applicant: Avnera Corporation
Inventor： Samuel J. Peters , Eric P. Etheridge , Victor Lee Hanson , Alexander C. Stange
IPC: H04L7/02
CPC classification number: H04L7/027 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
Abstract translation: 用于从输入数据流中恢复数据而不输入输入采样电路与输入数据流的同步的系统和技术确定输入采样（或帧）的计数，而不产生频率锁定到输入数据流的信号。 产生包括大于或等于输入数据流的预期频率的频率的第一时钟。 响应于在输入数据流中接收到的采样，采样计数递增，并且响应于第二时钟信号递减。 如果采样计数器的采样计数不等于预定采样计数值，并且如果采样计数等于预定采样计数值则阻塞第一时钟信号，则通过传递第一时钟信号来产生第二时钟信号。
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Patent Agency Ranking
公开(公告)号：US20190140816A1
公开(公告)日：2019-05-09
申请号：US16049474
申请日：2018-07-30
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero.
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公开(公告)号：US09832012B2
公开(公告)日：2017-11-28
申请号：US15484408
申请日：2017-04-11
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.
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公开(公告)号：US20140270028A1
公开(公告)日：2014-09-18
申请号：US13800557
申请日：2013-03-13
Applicant: Avnera Corporation
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hanson , Alexander C. Stange
IPC: H04L7/027
CPC classification number: H04L7/027 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
Abstract translation: 用于从输入数据流中恢复数据而不输入输入采样电路与输入数据流的同步的系统和技术确定输入采样（或帧）的计数，而不产生频率锁定到输入数据流的信号。 产生包括大于或等于输入数据流的预期频率的频率的第一时钟。 响应于在输入数据流中接收到的采样，采样计数递增，并且响应于第二时钟信号递减。 如果采样计数器的采样计数不等于预定采样计数值，并且如果采样计数等于预定采样计数值则阻塞第一时钟信号，则通过传递第一时钟信号来产生第二时钟信号。
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公开(公告)号：US20170222793A1
公开(公告)日：2017-08-03
申请号：US15484408
申请日：2017-04-11
Applicant: AVNERA CORPORATION
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A method can include a digital oversampler oversampling an input data stream, a rate generator selecting a frequency that is not less than an expected frequency of the input data stream, a rate generator clock of the rate generator outputting a clock signal that has the selected frequency, determining whether a sample receiver has received at least one sample of the input data stream from the digital oversampler, and, responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler, incrementing a sample counter by each received sample. The method can also include a sample rate converter accumulating samples from the sample receiver at the rate of a “toothless” clock signal, determining whether an output of the sample counter is greater than zero, and, responsive to a determination that the output of the sample counter is greater than zero, an AND gate passing the “toothless” clock signal to the sample rate converter.
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公开(公告)号：US09621336B1
公开(公告)日：2017-04-11
申请号：US14471324
申请日：2014-08-28
Applicant: Avnera Corporation
Inventor： Samuel J. Peters, II , Eric P. Etheridge , Victor Lee Hansen , Alexander C. Stange
IPC: H04L7/033
CPC classification number: H04L7/033 , G06F13/4295 , H04L7/0029 , H04L7/02
Abstract: A system and a technique for recovering data from an input data stream without synchronization of an input sampling circuit to the input data stream determines a count of incoming samples (or frames) without generating a signal that is frequency-locked to the input data stream. A first clock is generated comprising a frequency that is greater than or equal to an expected frequency of the input data stream. A sample count is incremented in response to a sample received in the input data stream, and is decremented in response to a second clock signal. The second clock is generated from the first clock signal by passing the first clock signal if the sample count of the sample counter does not equal a predetermined sample count value and by blocking the first clock signal if the sample count equals the predetermined sample count value.
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