- 专利标题： 3D field programmable gate array system with reset management and method of manufacture thereof
-
申请号： US15173507申请日： 2016-06-03
-
公开(公告)号： US09843328B1公开(公告)日： 2017-12-12
- 发明人: Ping Xiao
- 申请人： Altera Corporation
- 申请人地址： US CA San Jose
- 专利权人： Altera Corporation
- 当前专利权人： Altera Corporation
- 当前专利权人地址： US CA San Jose
- 主分类号： H03K19/017
- IPC分类号： H03K19/017 ; H03K19/177 ; H01L25/18 ; H01L23/00 ; H01L23/498 ; H01L25/065
摘要：
A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.
信息查询
