公开(公告)号：US09843328B1

公开(公告)日：2017-12-12

申请号：US15173507

申请日：2016-06-03

申请人： Altera Corporation

发明人： Ping Xiao

IPC分类号： H03K19/017 ,  H03K19/177 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L25/065

CPC分类号： H03K19/1774 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16155 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H03K17/223 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/17708

摘要： A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

公开(公告)号：US20130285717A1

公开(公告)日：2013-10-31

申请号：US13924153

申请日：2013-06-21

申请人： Altera Corporation

发明人： Ping Xiao ,  Weiyding Ding ,  Leo Min Maung

IPC分类号： H03L7/00

CPC分类号： H03L7/00 ,  G06F1/24 ,  H03K17/22 ,  H03K17/30 ,  H03K19/17736 ,  H03K19/17764

摘要： Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.

摘要翻译： 为诸如可编程逻辑器件集成电路的集成电路提供上电复位电路。 上电复位电路可以使用基于比较器的跳变点电压检测器来监视电源电压。 跳变点检测器可以使用电路从带隙参考电压产生跳变点电压。 控制器逻辑可以处理来自跳变点检测器的信号以产生相应的上电复位信号。 上电复位电路可以包含抑制电源电压尖峰噪声的噪声滤波器。 在测试期间可能会阻止上电复位电路的正常工作。 当带隙参考电压尚未达到所需的电平时，上电复位电路可能会被禁止。 上电复位电路可能对电源信号使用的上电顺序敏感或不敏感。 可以提供掉电检测阻塞电路以防止一个跳变点检测器的输出影响上电复位电路。

公开(公告)号：US20160352338A1

公开(公告)日：2016-12-01

申请号：US15220216

申请日：2016-07-26

申请人： Altera Corporation

发明人： Ping Xiao

IPC分类号： H03K19/177

CPC分类号： H03K19/17756 ,  H03K19/0008 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17776

摘要： An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

摘要翻译： 公开了一种用于配置和重新配置配置移位寄存器（CSR）部分重新配置区域的集成电路。 集成电路包括被划分成一组CSR部分重新配置区域的CSR链。 多路复用器电路被添加到每个PR区域的末端以允许PR区域被旁路或连接到下一个PR区域。 每个PR区域连接到有助于相应PR区域的CSR配置的PR电路。 PR电路包括区域使能电路和区域控制电路。 区域使能电路可以实现CSR PR区域的配置。 区域控制电路产生本地重新配置控制信号，以控制启用的CSR PR区域的配置操作。

公开(公告)号：US09425802B1

公开(公告)日：2016-08-23

申请号：US14723876

申请日：2015-05-28

申请人： Altera Corporation

发明人： Ping Xiao

IPC分类号： H03K19/177 ,  H03K19/00

CPC分类号： H03K19/17756 ,  H03K19/0008 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17776

摘要： An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

摘要翻译： 公开了一种用于配置和重新配置配置移位寄存器（CSR）部分重新配置区域的集成电路。 集成电路包括被划分成一组CSR部分重新配置区域的CSR链。 多路复用器电路被添加到每个PR区域的末端以允许PR区域被旁路或连接到下一个PR区域。 每个PR区域连接到有助于相应PR区域的CSR配置的PR电路。 PR电路包括区域使能电路和区域控制电路。 区域使能电路可以实现CSR PR区域的配置。 区域控制电路产生本地重新配置控制信号，以控制启用的CSR PR区域的配置操作。

公开(公告)号：US09374094B1

公开(公告)日：2016-06-21

申请号：US14470901

申请日：2014-08-27

申请人： Altera Corporation

发明人： Ping Xiao

IPC分类号： H03K19/017 ,  H03K19/08 ,  H03K19/0175 ,  H01L25/16 ,  H03K19/177 ,  H03K17/22

CPC分类号： H03K19/1774 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16155 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/18161 ,  H03K17/223 ,  H03K19/0175 ,  H03K19/08 ,  H03K19/17708

摘要： A 3D field programmable gate array (FPGA) system, and method of manufacture therefor, includes: a field programmable gate array (FPGA) die having a configurable power on reset (POR) unit; a heterogeneous integrated circuit die coupled to the FPGA die; and a 3D power on reset (POR) output configured by the configurable POR unit for initializing the FPGA die and the heterogeneous integrated circuit die.

摘要翻译： 3D现场可编程门阵列（FPGA）系统及其制造方法包括：具有可配置上电复位（POR）单元的现场可编程门阵列（FPGA）管芯; 耦合到FPGA管芯的异质集成电路管芯; 以及由可配置POR单元配置的用于初始化FPGA管芯和异质集成电路管芯的3D上电复位（POR）输出。

公开(公告)号：US09859897B2

公开(公告)日：2018-01-02

申请号：US15220216

申请日：2016-07-26

申请人： Altera Corporation

发明人： Ping Xiao

IPC分类号： H03K19/177 ,  H03K19/00

CPC分类号： H03K19/17756 ,  H03K19/0008 ,  H03K19/17728 ,  H03K19/17744 ,  H03K19/1776 ,  H03K19/17776

摘要： An integrated circuit for configuring and reconfiguring a configuration shift register (CSR) partial reconfiguration region is disclosed. The integrated circuit includes a CSR chain that is partitioned into a group of CSR partial reconfiguration regions. A multiplexer circuit is added to the end of each PR region to allow the PR region to be bypassed or connected to the next PR region. Each PR region is connected to a PR circuit that facilitates the CSR configuration of the respective PR region. The PR circuit includes region enable circuitry and region control circuitry. Region enable circuitry enables the configuration of the CSR PR region. Region control circuitry generates local reconfiguration control signals to control the configuration operation of the enabled CSR PR region.

公开(公告)号：US08754680B2

公开(公告)日：2014-06-17

申请号：US13924153

申请日：2013-06-21

申请人： Altera Corporation

发明人： Ping Xiao ,  Weiyding Ding ,  Leo Min Maung

IPC分类号： H03L7/00

CPC分类号： H03L7/00 ,  G06F1/24 ,  H03K17/22 ,  H03K17/30 ,  H03K19/17736 ,  H03K19/17764

摘要： Power-on-reset circuitry is provided for integrated circuits such as programmable logic device integrated circuits. The power-on-reset circuitry may use comparator-based trip point voltage detectors to monitor power supply voltages. The trip point detectors may use circuitry to produce trip point voltages from a bandgap reference voltage. Controller logic may process signals from the trip point detectors to produce a corresponding power-on-reset signal. The power-on-reset circuitry may contain a noise filter that suppresses noise from power supply voltage spikes. Normal operation of the power-on-reset circuitry may be blocked during testing. The power-on-reset circuitry may be disabled when the bandgap reference voltage has not reached a desired level. The power-on-reset circuitry may be sensitive or insensitive to the power-up sequence used by the power supply signals. Brownout detection blocking circuitry may be provided to prevent the output from one of the trip point detectors from influencing the power-on-reset circuitry.

摘要翻译： 为诸如可编程逻辑器件集成电路的集成电路提供上电复位电路。 上电复位电路可以使用基于比较器的跳变点电压检测器来监视电源电压。 跳变点检测器可以使用电路从带隙参考电压产生跳变点电压。 控制器逻辑可以处理来自跳变点检测器的信号以产生相应的上电复位信号。 上电复位电路可以包含抑制电源电压尖峰噪声的噪声滤波器。 在测试期间可能会阻止上电复位电路的正常工作。 当带隙参考电压尚未达到所需的电平时，上电复位电路可能会被禁止。 上电复位电路可能对电源信号使用的上电顺序敏感或不敏感。 可以提供掉电检测阻塞电路以防止一个跳变点检测器的输出影响上电复位电路。