- 专利标题: Semiconductor device and method of forming conductive vias using backside via reveal and selective passivation
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申请号: US14222547申请日: 2014-03-21
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公开(公告)号: US09865524B2公开(公告)日: 2018-01-09
- 发明人: Duk Ju Na , Chang Beom Yong , Pandi C. Marimuthu
- 申请人: STATS ChipPAC, Ltd.
- 申请人地址: SG Singapore
- 专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人: STATS ChipPAC Pte. Ltd.
- 当前专利权人地址: SG Singapore
- 代理机构: Patent Law Group: Atkins and Associates, P.C.
- 代理商 Robert D. Atkins
- 主分类号: H01L23/48
- IPC分类号: H01L23/48 ; H01L23/00 ; H01L21/768 ; H01L23/31 ; H01L21/66
摘要:
A semiconductor device includes a plurality of semiconductor die and a plurality of conductive vias formed in the semiconductor die. An insulating layer is formed over the semiconductor die while leaving the conductive vias exposed. An interconnect structure is formed over the insulating layer and conductive vias. The insulating layer is formed using electrografting or oxidation. An under bump metallization is formed over the conductive vias. A portion of the semiconductor die is removed to expose the conductive vias. The interconnect structure is formed over two or more of the conductive vias. A portion of the semiconductor die is removed to leave the conductive vias with a height greater than a height of the semiconductor die. A second insulating layer is formed over the first insulating layer. A portion of the second insulating layer is removed to expose the conductive via.
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