A system, processor, and method to record the interleavings of shared memory accesses in the presence of complex multi-operation instructions. An extension to instruction atomicity (IA) is disclosed that makes it possible for software to infer partial information about a multi-operation execution if the hardware has recorded a dependency due to an instruction atomicity violation (IAV). By monitoring the progress of a multi-operation instruction, the need for complex multi-operation emulation is unnecessary.