Invention Grant
- Patent Title: Memory architecture and cell design employing two access transistors
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Application No.: US14277282Application Date: 2014-05-14
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Publication No.: US09875795B2Publication Date: 2018-01-23
- Inventor: Jun Liu
- Applicant: Micron Technology, Inc.
- Applicant Address: US ID Boise
- Assignee: Micron Technology, Inc.
- Current Assignee: Micron Technology, Inc.
- Current Assignee Address: US ID Boise
- Agency: Schwegman Lundberg & Woessner, P.A.
- Main IPC: G11C13/00
- IPC: G11C13/00 ; G11C11/16 ; H01L27/24 ; G11C17/16 ; H01L45/00
Abstract:
Some embodiments include an improved memory array architecture and memory cell design. In one of such embodiments, a memory cell may comprise a memory element to store a logic state and two access transistors coupled to the memory element to access the logic state of the memory element. Other embodiments are described.
Public/Granted literature
- US20140247640A1 MEMORY ARCHITECTURE AND CELL DESIGN EMPLOYING TWO ACCESS TRANSISTORS Public/Granted day:2014-09-04
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