Invention Grant
- Patent Title: Chip package and manufacturing method thereof
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Application No.: US15358098Application Date: 2016-11-21
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Publication No.: US09875912B2Publication Date: 2018-01-23
- Inventor: Yen-Shih Ho , Hsiao-Lan Yeh , Chia-Sheng Lin , Yi-Ming Chang , Po-Han Lee , Hui-Hsien Wu , Jyun-Liang Wu
- Applicant: XINTEC INC.
- Applicant Address: TW Taoyuan
- Assignee: XINTEC INC.
- Current Assignee: XINTEC INC.
- Current Assignee Address: TW Taoyuan
- Agency: Liu & Liu
- Main IPC: H01L23/48
- IPC: H01L23/48 ; H01L23/52 ; H01L29/40 ; H01L21/56 ; H01L21/683 ; H01L21/78 ; G06K9/00 ; H01L23/31

Abstract:
A chip package includes a chip, a first adhesive layer, a second adhesive layer, and a protection cap. The chip has a sensing area, a first surface, a second surface that is opposite to the first surface, and a side surface adjacent to the first and second surfaces. The sensing area is located on the first surface. The first adhesive layer covers the first surface of the chip. The second adhesive layer is located on the first adhesive layer, such that the first adhesive layer is between the first surface and the second adhesive layer. The protection cap has a bottom board and a sidewall that surrounds the bottom board. The bottom board covers the second adhesive layer, and the sidewall covers the side surface of the chip.
Public/Granted literature
- US20170148694A1 CHIP PACKAGE AND MANUFACTURING METHOD THEREOF Public/Granted day:2017-05-25
Information query
IPC分类: