公开(公告)号：US11476293B2

公开(公告)日：2022-10-18

申请号：US16950810

申请日：2020-11-17

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Tsang-Yu Liu ,  Po-Han Lee

IPC: H01L27/146 ,  H01L23/00

Abstract: A manufacturing method of a chip package includes forming a temporary bonding layer on a carrier; forming an encapsulation layer on a top surface of a wafer or on the temporary bonding layer; bonding the carrier to the wafer, in which the encapsulation layer covers a sensor and a conductive pad of the wafer; patterning a bottom surface of the wafer to form a through hole, in which the conductive pad is exposed through the through hole; forming an isolation layer on the bottom surface of the wafer and a sidewall of the through hole; forming a redistribution layer on the isolation layer and the conductive pad that is in the through hole; forming a passivation layer on the isolation layer and the redistribution layer; and removing the temporary bonding layer and the carrier.

公开(公告)号：US11038077B2

公开(公告)日：2021-06-15

申请号：US16291637

申请日：2019-03-04

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Po-Han Lee ,  Chien-Min Lin ,  Yi-Rong Ho

IPC: H01L31/12 ,  H01L31/02 ,  H01L31/0203 ,  H01L31/0216 ,  H01L31/18 ,  H01L31/028

Abstract: A chip package includes a chip, a sidewall structure that has a first light-shielding layer, a second light-shielding layer, and a cover. The chip has a light emitter and a light receiver that are located on a top surface of the chip. The sidewall structure is located on the top surface of the chip and has two aperture areas. The light emitter and the light receiver are respectively located in the two aperture areas. The sidewall structure surrounds the light emitter and the light receiver, and at least one surface of the sidewall structure has the first light-shielding layer. The second light-shielding layer is located between the chip and the sidewall structure. The cover is located on a surface of the sidewall structure facing away from the chip, and at least covers the light receiver and the sidewall structure that surrounds the light receiver.

公开(公告)号：US09640683B2

公开(公告)日：2017-05-02

申请号：US14640307

申请日：2015-03-06

Applicant: XINTEC INC.

Inventor： Wei-Luen Suen ,  Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/18 ,  H01L31/0236 ,  H01L31/02 ,  H01L31/0203 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L23/3114 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/11

Abstract: A semiconductor structure includes a silicon substrate, a protection layer, an electrical pad, an isolation layer, a redistribution layer, a conductive layer, a passivation layer, and a conductive structure. The silicon substrate has a concave region, a step structure, a tooth structure, a first surface, and a second surface opposite to the first surface. The step structure and the tooth structure surround the concave region. The step structure has a first oblique surface, a third surface, and a second oblique surface facing the concave region and connected in sequence. The protection layer is located on the first surface of the silicon substrate. The electrical pad is located in the protection layer and exposed through the concave region. The isolation layer is located on the first and second oblique surfaces, the second and third surfaces of the step structure, and the tooth structure.

公开(公告)号：US09214579B2

公开(公告)日：2015-12-15

申请号：US14534684

申请日：2014-11-06

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L31/0232 ,  H01L31/02 ,  H01L31/18 ,  H01L31/0236

CPC classification number: H01L31/02327 ,  H01L21/561 ,  H01L21/76898 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/525 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L31/02002 ,  H01L31/0203 ,  H01L31/02363 ,  H01L31/1804 ,  H01L2224/02331 ,  H01L2224/02372 ,  H01L2224/02381 ,  H01L2224/0346 ,  H01L2224/0348 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05155 ,  H01L2224/05569 ,  H01L2224/05582 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/113 ,  H01L2224/13022 ,  H01L2924/00014 ,  H01L2224/13099

Abstract: A manufacturing method of a semiconductor structure includes the following steps. A wafer structure having a silicon substrate and a protection layer is provided. An electrical pad on the protection layer is exposed through the concave region of the silicon substrate. An isolation layer is formed on the sidewall of the silicon substrate surrounding the concave region and a surface of the silicon substrate facing away from the protection layer. A redistribution layer is formed on the isolation layer and the electrical pad. A passivation layer is formed on the redistribution layer. The passivation layer is patterned to form a first opening therein. A first conductive layer is formed on the redistribution layer exposed through the first opening. A conductive structure is arranged in the first opening, such that the conductive structure is in electrical contact with the first conductive layer.

Abstract translation: 半导体结构的制造方法包括以下步骤。 提供了具有硅衬底和保护层的晶片结构。 保护层上的电焊盘通过硅衬底的凹入区露出。 在硅基板的侧壁上形成隔离层，该隔离层包围该凹陷区域以及该硅基板的远离该保护层的表面。 在隔离层和电焊盘上形成再分布层。 在再分布层上形成钝化层。 图案化钝化层以在其中形成第一开口。 在通过第一开口露出的再分布层上形成第一导电层。 导电结构布置在第一开口中，使得导电结构与第一导电层电接触。

公开(公告)号：US09305842B2

公开(公告)日：2016-04-05

申请号：US14592818

申请日：2015-01-08

Applicant: XINTEC INC.

Inventor： Chia-Sheng Lin ,  Po-Han Lee

IPC: H01L21/768 ,  H01L21/48 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31 ,  H01L27/146

CPC classification number: H01L21/76898 ,  H01L21/481 ,  H01L21/76897 ,  H01L23/3178 ,  H01L23/3192 ,  H01L23/5389 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L24/19 ,  H01L24/94 ,  H01L27/14618 ,  H01L27/14636 ,  H01L2224/02372 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/04105 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/06181 ,  H01L2224/1132 ,  H01L2224/11462 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/20 ,  H01L2224/94 ,  H01L2224/97 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/00

Abstract: A chip package and a fabrication method thereof are provided. The chip package includes a semiconductor substrate, having a first surface and an opposing second surface. A spacer is disposed under the second surface of the semiconductor substrate and a cover plate is disposed under the spacer. A recessed portion is formed adjacent to a sidewall of the semiconductor substrate, extending from the first surface of the semiconductor substrate to at least the spacer. Then, a protection layer is disposed over the first surface of the semiconductor substrate and in the recessed portion.

Abstract translation: 提供了芯片封装及其制造方法。 芯片封装包括具有第一表面和相对的第二表面的半导体衬底。 间隔件设置在半导体衬底的第二表面下方，并且覆盖板设置在间隔件下方。 形成与半导体衬底的侧壁相邻的凹部，从半导体衬底的第一表面延伸到至少间隔件。 然后，保护层设置在半导体衬底的第一表面和凹部中。

公开(公告)号：US08872196B2

公开(公告)日：2014-10-28

申请号：US13720627

申请日：2012-12-19

Applicant: Xintec Inc.

Inventor： Po-Han Lee ,  Chien-Hung Liu

IPC: H01L31/12 ,  H01L31/18

CPC classification number: H01L31/12 ,  H01L31/1876

Abstract: An embodiment of the invention provides a chip package which includes: a semiconductor substrate having a first surface and a second surface; a sensor region formed in the semiconductor substrate; a light emitting device disposed on the second surface of the semiconductor substrate; at least one first conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the sensor region; at least one second conducting bump disposed on the first surface of the semiconductor substrate and electrically connected to the light emitting device; and an insulating layer located on the semiconductor substrate to electrically insulate the semiconductor substrate from the at least one first conducting bump and the at least one second conducting bump.

Abstract translation: 本发明的实施例提供一种芯片封装，其包括：具有第一表面和第二表面的半导体衬底; 形成在所述半导体衬底中的传感器区域; 设置在所述半导体衬底的第二表面上的发光器件; 至少一个第一导电凸块，设置在所述半导体衬底的所述第一表面上并电连接到所述传感器区域; 设置在所述半导体衬底的所述第一表面上并电连接到所述发光器件的至少一个第二导电凸块; 以及绝缘层，其位于所述半导体衬底上以使所述半导体衬底与所述至少一个第一导电凸块和所述至少一个第二导电凸块电绝缘。

公开(公告)号：US11387201B2

公开(公告)日：2022-07-12

申请号：US17023199

申请日：2020-09-16

Applicant: XINTEC INC.

Inventor： Po-Han Lee ,  Chia-Ming Cheng ,  Jiun-Yen Lai ,  Ming-Chung Chung ,  Wei-Luen Suen

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/552 ,  H01L21/3213

Abstract: A chip package includes a semiconductor substrate, a supporting element, an antenna layer, and a redistribution layer. The semiconductor substrate has an inclined sidewall and a conductive pad that protrudes from the inclined sidewall. The supporting element is located on the semiconductor substrate, and has a top surface facing away from the semiconductor substrate, and has an inclined sidewall adjoining the top surface. The antenna layer is located on the top surface of the supporting element. The redistribution layer is located on the inclined sidewall of the supporting element, and is in contact with a sidewall of the conductive pad and an end of the antenna.

公开(公告)号：US10446504B2

公开(公告)日：2019-10-15

申请号：US15980577

申请日：2018-05-15

Applicant: XINTEC INC.

Inventor： Chia-Ming Cheng ,  Po-Han Lee ,  Wei-Chung Yang ,  Kuan-Jung Wu ,  Shu-Ming Chang

IPC: H01L23/52 ,  H01L23/00 ,  H01L25/16 ,  H01L21/56 ,  H01L23/31 ,  H01L23/04 ,  H01L27/146

Abstract: A chip package is provided. A first bonding structure is disposed on a first redistribution layer (RDL). A first chip includes a sensing region and a conductive pad that are adjacent to an active surface. The first chip is bonded onto the first RDL through the first bonding structure. The first bonding structure is disposed between the conductive pad and the first RDL. A molding layer covers the first RDL and surrounds the first chip. A second RDL is disposed on the molding layer and the first chip and is electrically connected to the first RDL. A second chip is stacked on a non-active surface of the first chip and is electrically connected to the first chip through the second RDL, the first RDL, and the first bonding structure. A method of forming the chip package is also provided.

公开(公告)号：US10424540B2

公开(公告)日：2019-09-24

申请号：US15724058

申请日：2017-10-03

Applicant: XINTEC INC.

Inventor： Yen-Shih Ho ,  Po-Han Lee ,  Chia-Ming Cheng ,  Hsin-Yen Lin

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/498 ,  H01L23/00 ,  H01L23/495 ,  H01L27/146

Abstract: A chip package including a substrate having an upper surface, a lower surface, and a sidewall surface that is at the edge of the substrate is provided. The substrate includes a sensor device therein and adjacent to the upper surface thereof. The chip package further includes light-shielding layer disposed over the sidewall surface of the substrate and extends along the edge of the substrate to surround the sensor device. The chip package further includes a cover plate disposed over the upper surface of the substrate and a spacer layer disposed between the substrate and the cover plate. A method of forming the chip package is also provided.

公开(公告)号：US10096635B2

公开(公告)日：2018-10-09

申请号：US14819138

申请日：2015-08-05

Applicant: XINTEC INC.

Inventor： Wei-Ming Chien ,  Po-Han Lee ,  Tsang-Yu Liu ,  Yen-Shih Ho

IPC: H01L27/146

Abstract: A semiconductor structure includes a chip, a light transmissive plate, a spacer, and a light-shielding layer. The chip has an image sensor, a first surface and a second surface opposite to the first surface. The image sensor is located on the first surface. The light transmissive plate is disposed on the first surface and covers the image sensor. The spacer is between the light transmissive plate and the first surface, and surrounds the image sensor. The light-shielding layer is located on the first surface between the spacer and the image sensor.