- 专利标题: Method of obfuscating digital logic circuits using threshold voltage
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申请号: US15390970申请日: 2016-12-27
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公开(公告)号: US09876503B2公开(公告)日: 2018-01-23
- 发明人: Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
- 申请人: Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
- 申请人地址: US AZ Scottsdale
- 专利权人: Arixona Board of Regents on Behalf of Arizona State University
- 当前专利权人: Arixona Board of Regents on Behalf of Arizona State University
- 当前专利权人地址: US AZ Scottsdale
- 代理机构: Withrow & Terranova, P.L.L.C.
- 主分类号: H03K19/20
- IPC分类号: H03K19/20 ; H03K19/08 ; H03K19/096 ; H03K19/21
摘要:
A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.
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