Invention Grant
- Patent Title: Self-latch sense timing in a one-time-programmable memory architecture
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Application No.: US15247352Application Date: 2016-08-25
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Publication No.: US09881687B2Publication Date: 2018-01-30
- Inventor: Yunchen Qiu , David J. Toops , Harold L. Davis
- Applicant: Texas Instruments Incorporated
- Applicant Address: US TX Dallas
- Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee: TEXAS INSTRUMENTS INCORPORATED
- Current Assignee Address: US TX Dallas
- Agent Kenneth Liu; Charles A. Brill; Frank D. Cimino
- Main IPC: G11C17/18
- IPC: G11C17/18 ; G11C17/16

Abstract:
A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.
Public/Granted literature
- US20170178742A1 Self-Latch Sense Timing in a One-Time-Programmable Memory Architecture Public/Granted day:2017-06-22
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