公开(公告)号：US20240304223A1

公开(公告)日：2024-09-12

申请号：US18667059

申请日：2024-05-17

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  David J. Toops

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  H03K19/173

CPC classification number: G11C7/062 ,  G11C7/1069 ,  G11C7/12 ,  H03K19/1737

Abstract: A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

公开(公告)号：US20230267969A1

公开(公告)日：2023-08-24

申请号：US17877954

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  David J. Toops

IPC: G11C7/06 ,  G11C7/12 ,  G11C7/10 ,  H03K19/173

CPC classification number: G11C7/062 ,  G11C7/12 ,  G11C7/1069 ,  H03K19/1737

Abstract: A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

公开(公告)号：US10192629B2

公开(公告)日：2019-01-29

申请号：US15871381

申请日：2018-01-15

Applicant: Texas Instruments Incorporated

Inventor： Yunchen Qiu ,  David J. Toops ,  Harold L. Davis

IPC: G11C17/18 ,  G11C17/16 ,  G11C7/08 ,  G11C7/22

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.

公开(公告)号：US10854265B2

公开(公告)日：2020-12-01

申请号：US16404118

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David J. Toops

IPC: G11C11/22

Abstract: An example memory circuit for reading and/or writing FRAM memory includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.

公开(公告)号：US20170256299A1

公开(公告)日：2017-09-07

申请号：US15057475

申请日：2016-03-01

Applicant: Texas Instruments Incorporated

Inventor： David J. Toops

IPC: G11C11/22

CPC classification number: G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2293

Abstract: Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.

公开(公告)号：US12027229B2

公开(公告)日：2024-07-02

申请号：US17877954

申请日：2022-07-31

Applicant: Texas Instruments Incorporated

Inventor： Suresh Balasubramanian ,  David J. Toops

IPC: G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  H03K19/173

CPC classification number: G11C7/062 ,  G11C7/1069 ,  G11C7/12 ,  H03K19/1737

Abstract: A semiconductor device includes a ROM, a differential sense amplifier and a multiplexer logic circuit. The ROM has memory cells in rows along word lines and columns along bit lines, and a reference column having reference transistors along a reference bit line. The multiplexer logic circuit couples a selected bit line to a first differential amplifier input and couples the reference bit line to the second differential amplifier input and controls a reference current of the reference bit line to be between a first bit line current of a programmed memory cell and a second bit line current of an unprogrammed memory cell.

公开(公告)号：US11558046B2

公开(公告)日：2023-01-17

申请号：US16035394

申请日：2018-07-13

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David J. Toops

IPC: H03K5/133 ,  H03K5/13 ,  H03K5/159 ,  H03K5/00

Abstract: A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the precharge transistor having a negative temperature coefficient to thereby form a node. A capacitive device and an inverter are coupled to the node. The inverter produces an output signal. Responsive to the input signal having a first polarity, the precharge transistor is configured to be turned on and the discharge transistor is configured to be turned off to thereby cause current to flow through the precharge transistor to the capacitive device to thereby charge the capacitive device. Responsive to the input signal having a second polarity, the precharge and discharge transistors are configured to change state to thereby cause charge from the capacitive device to discharge through the resistor and through the discharge transistor. The voltage on the node decays to a level which eventually causes the inverter's output to change state.

公开(公告)号：US20210082489A1

公开(公告)日：2021-03-18

申请号：US17108041

申请日：2020-12-01

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David J. Toops

IPC: G11C11/22

Abstract: Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.

公开(公告)号：US20190333561A1

公开(公告)日：2019-10-31

申请号：US16404118

申请日：2019-05-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： David J. Toops

IPC: G11C11/22

Abstract: Methods and apparatus for reading and/or writing FRAM memory are disclosed. An example memory circuit includes a controller to output a signal to an input of a driver; a transistor coupled an output of the driver; the driver to, in response to receiving the signal, output a first voltage to the transistor; and the transistor to, in response to receiving the first voltage, output a second voltage to a bit cell after a transistor delay, the transistor selected based on a size of the memory circuit.

公开(公告)号：US20170178742A1

公开(公告)日：2017-06-22

申请号：US15247352

申请日：2016-08-25

Applicant: Texas Instruments Incorporated

Inventor： Yunchen Qiu ,  David J. Toops ,  Harold L. Davis

IPC: G11C17/18 ,  G11C17/16

CPC classification number: G11C17/18 ,  G11C7/08 ,  G11C7/227 ,  G11C17/16

Abstract: A programmable memory including a self-latching read data path. A sense amplifier senses the voltage level at a bit line, the bit line communicating the data state of a selected memory cell in its associated column. A data latch coupled to the output of the sense amplifier passes the sensed data state. Set-reset logic is provided that receives the output of the data latch in the read data path and, in response to a transition of the data state in a read cycle, latches the data latch and isolates it from the sense amplifier. The set-reset logic resets the data latch at the start of the next read cycle. In some embodiments, a timer is provided so that the latch is reset after a time-out period in a long read cycle in which no data transition occurs.