Invention Grant
- Patent Title: Method of making split gate non-volatile memory cell with 3D FinFET structure
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Application No.: US15453829Application Date: 2017-03-08
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Publication No.: US09887206B2Publication Date: 2018-02-06
- Inventor: Chien-Sheng Su , Jeng-Wei Yang , Man-Tang Wu , Chun-Ming Chen , Hieu Van Tran , Nhan Do
- Applicant: Silicon Storage Technology, Inc.
- Applicant Address: US CA San Jose
- Assignee: Silicon Storage Technology, Inc.
- Current Assignee: Silicon Storage Technology, Inc.
- Current Assignee Address: US CA San Jose
- Agency: DLA Piper LLP (US)
- Main IPC: H01L21/336
- IPC: H01L21/336 ; H01L27/11521 ; H01L21/28 ; H01L29/66 ; H01L29/08 ; H01L29/78 ; H01L29/788
Abstract:
A non-volatile memory cell, and method of making, that includes a semiconductor substrate having a fin shaped upper surface with a top surface and two side surfaces. Source and drain regions are formed in the fin shaped upper surface portion with a channel region there between. A conductive floating gate includes a first portion extending along a first portion of the top surface, and second and third portions extending along first portions of the two side surfaces, respectively. A conductive control gate includes a first portion extending along a second portion of the top surface, second and third portions extending along second portions of the two side surfaces respectively, a fourth portion extending up and over at least some of the floating gate first portion, and fifth and sixth portions extending out and over at least some of the floating gate second and third portions respectively.
Public/Granted literature
- US20170179141A1 Method Of Making Split Gate Non-volatile Memory Cell With 3D FINFET Structure Public/Granted day:2017-06-22
Information query
IPC分类:
