Invention Grant
- Patent Title: Method and apparatus to increase the speed of the load access and data return speed path using early lower address bits
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Application No.: US14281663Application Date: 2014-05-19
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Publication No.: US09891915B2Publication Date: 2018-02-13
- Inventor: Mohammad A. Abdallah , Ravishankar Rao
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F9/30 ; G06F12/1045

Abstract:
A microprocessor implemented method for resolving dependencies for a load instruction in a load store queue (LSQ) is disclosed. The method comprises initiating a computation of a virtual address corresponding to the load instruction in a first clock cycle. It also comprises transmitting early calculated lower address bits of the virtual address to a load store queue (LSQ) in the same cycle as the initiating. Finally, it comprises performing a partial match in the LSQ responsive to and using the lower address bits to find a prior aliasing store, wherein the prior aliasing store stores to a same address as the load instruction.
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