公开(公告)号：US10289419B2

公开(公告)日：2019-05-14

申请号：US15673286

申请日：2017-08-09

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Mandeep Singh

IPC: G06F9/38

Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

公开(公告)号：US09753734B2

公开(公告)日：2017-09-05

申请号：US15215004

申请日：2016-07-20

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Mandeep Singh

IPC: G06F9/30 ,  G06F9/40 ,  G06F9/38

CPC classification number: G06F9/3855 ,  G06F9/3834 ,  G06F9/3857

Abstract: A method for sorting elements in hardware structures is disclosed. The method comprises selecting a plurality of elements to order from an unordered input queue (UIQ) within a predetermined range in response to finding a match between at least one most significant bit of the predetermined range and corresponding bits of a respective identifier associated with each of the plurality of elements. The method further comprises presenting each of the plurality of elements to a respective multiplexer. Further the method comprises generating a select signal for an enabled multiplexer in response to finding a match between at least one least significant bit of a respective identifier associated with each of the plurality of elements and a port number of the ordered queue. Finally, the method comprises forwarding a packet associated with a selected element identifier to a matching port number of the ordered queue from the enabled multiplexer.

公开(公告)号：US10514926B2

公开(公告)日：2019-12-24

申请号：US14211476

申请日：2014-03-14

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/455

Abstract: A microprocessor implemented method for performing early dependency resolution and data forwarding is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each current guest branch instruction in the native address space fetched during execution, performing (a) determining a youngest prior guest branch target stored in a guest branch target register, wherein the guest branch register is operable to speculatively store a plurality of prior guest branch targets corresponding to prior guest branch instructions; (b) determining a current branch target for a respective current guest branch instruction by adding an offset value for the respective current guest branch instruction to the youngest prior guest branch target; and (c) creating an entry in the guest branch target register for the current branch target.

公开(公告)号：US10467010B2

公开(公告)日：2019-11-05

申请号：US14209736

申请日：2014-03-13

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Mandeep Singh

IPC: G06F9/38 ,  G06F9/30

Abstract: A method for performing memory disambiguation in an out-of-order microprocessor pipeline is disclosed. The method comprises storing a tag with a load operation, wherein the tag is an identification number representing a store instruction nearest to the load operation, wherein the store instruction is older with respect to the load operation and wherein the store has potential to result in a RAW violation in conjunction with the load operation. The method also comprises issuing the load operation from an instruction scheduling module. Further, the method comprises acquiring data for the load operation speculatively after the load operation has arrived at a load store queue module. Finally, the method comprises determining if an identification number associated with a last contiguous issued store with respect to the load operation is equal to or greater than the tag and gating a validation process for the load operation in response to the determination.

公开(公告)号：US10228950B2

公开(公告)日：2019-03-12

申请号：US14211655

申请日：2014-03-14

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah

IPC: G06F9/38 ,  G06F9/455 ,  G06F9/30

Abstract: A microprocessor implemented method for maintaining a guest return address stack in an out-of-order microprocessor pipeline is disclosed. The method comprises mapping a plurality of instructions in a guest address space into a corresponding plurality of instructions in a native address space. For each function call instruction in the native address space fetched during execution, the method also comprises performing the following: (a) pushing a current entry into a guest return address stack (GRAS) responsive to a function call, wherein the GRAS is maintained at the fetch stage of the pipeline, and wherein the current entry comprises information regarding both a guest target return address and a corresponding native target return address associated with the function call; (b) popping the current entry from the GRAS in response to processing a return instruction; and (c) fetching instructions from the native target return address in the current entry after the popping from the GRAS.

公开(公告)号：US09965277B2

公开(公告)日：2018-05-08

申请号：US14567797

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah

IPC: G06F9/312 ,  G06F5/14 ,  G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F5/14 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3824 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F2205/063 ,  G06F2205/064

Abstract: An out of order processor. The processor includes a virtual load store queue for allocating a plurality of loads and a plurality of stores, wherein more loads and more stores can be accommodated beyond an actual physical size of the load store queue of the processor; wherein the processor allocates other instructions besides loads and stores beyond the actual physical size limitation of the load/store queue; and wherein the other instructions can be dispatched and executed even though intervening loads or stores do not have spaces in the load store queue.

公开(公告)号：US10810014B2

公开(公告)日：2020-10-20

申请号：US16251941

申请日：2019-01-18

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/455

Abstract: A microprocessor implemented method of speculatively maintaining a guest return address stack (GRAS) in a fetch stage of a microprocessor pipeline. The method includes mapping instructions in a guest address space to corresponding instructions in a native address space. For each of one or more function calls made in the native address space, performing the following: (a) pushing a current entry into the GRAS responsive to the function call, where the current entry includes a guest target return address and a corresponding native target return address associated with the function call; (b) popping the current entry from the GRAS responsive to processing a return instruction; (c) comparing the current entry with an entry popped from a return address stack (RAS) maintained at a later stage of the pipeline; and (d) responsive to a mismatch, fetching instructions from the return address in the entry popped from the RAS.

公开(公告)号：US10289605B2

公开(公告)日：2019-05-14

申请号：US15853323

申请日：2017-12-22

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah

IPC: G06F9/30 ,  G06F15/80 ,  G06F7/533 ,  G06F9/38 ,  G06F7/483 ,  G06F7/53 ,  G06F7/544

Abstract: A matrix of execution blocks form a set of rows and columns. The rows support parallel execution of instructions and the columns support execution of dependent instructions. The matrix of execution blocks process a single block of instructions specifying parallel and dependent instructions.

公开(公告)号：US10019263B2

公开(公告)日：2018-07-10

申请号：US14569551

申请日：2014-12-12

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/3017 ,  G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857

Abstract: In a processor, a disambiguation-free out of order load store queue method. The method includes implementing a memory resource that can be accessed by a plurality of asynchronous cores; implementing a store retirement buffer, wherein stores from a store queue have entries in the store retirement buffer in original program order; and implementing speculative execution, wherein results of speculative execution can be saved in the store retirement/reorder buffer as a speculative state. The method further includes, upon dispatch of a subsequent load from a load queue, searching the store retirement buffer for address matching; and, in cases where there are a plurality of address matches, locating a correct forwarding entry by scanning for the store retirement buffer for a first match, and forwarding data from the first match to the subsequent load. Once speculative outcomes are known, the speculative state is retired to memory.

公开(公告)号：US09990198B2

公开(公告)日：2018-06-05

申请号：US14567731

申请日：2014-12-11

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Gregory A. Woods

IPC: G06F9/312 ,  G06F9/38 ,  G06F9/45 ,  G06F9/30

CPC classification number: G06F9/3005 ,  G06F8/443 ,  G06F8/445 ,  G06F9/30032 ,  G06F9/30043 ,  G06F9/30145 ,  G06F9/3017 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3855

Abstract: A method for forwarding data from the store instructions to a corresponding load instruction in an out of order processor. The method includes accessing an incoming sequence of instructions, and of said sequence of instructions, splitting store instructions into a store address instruction and a store data instruction, wherein the store address performs address calculation and fetch, and wherein the store data performs a load of register contents to a memory address. The method further includes, of said sequence of instructions, splitting load instructions into a load address instruction and a load data instruction, wherein the load address performs address calculation and fetch, and wherein the load data performs a load of memory address contents into a register, and reordering the store address and load address instructions earlier and further away from LD/SD the instruction sequence to enable earlier dispatch and execution of the loads and the stores.