公开(公告)号：US09891915B2

公开(公告)日：2018-02-13

申请号：US14281663

申请日：2014-05-19

Applicant: Intel Corporation

Inventor： Mohammad A. Abdallah ,  Ravishankar Rao

IPC: G06F12/00 ,  G06F9/30 ,  G06F12/1045

CPC classification number: G06F9/30043 ,  G06F12/1054

Abstract: A microprocessor implemented method for resolving dependencies for a load instruction in a load store queue (LSQ) is disclosed. The method comprises initiating a computation of a virtual address corresponding to the load instruction in a first clock cycle. It also comprises transmitting early calculated lower address bits of the virtual address to a load store queue (LSQ) in the same cycle as the initiating. Finally, it comprises performing a partial match in the LSQ responsive to and using the lower address bits to find a prior aliasing store, wherein the prior aliasing store stores to a same address as the load instruction.

公开(公告)号：US10740126B2

公开(公告)日：2020-08-11

申请号：US16166010

申请日：2018-10-19

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ankur Groen ,  Erika Gunadi ,  Mandeep Singh ,  Ravishankar Rao

IPC: G06F9/32 ,  G06F12/08 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/1036 ,  G06F9/38

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

公开(公告)号：US10248570B2

公开(公告)日：2019-04-02

申请号：US15862496

申请日：2018-01-04

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ravishankar Rao ,  Karthikeyan Avudaiyappan

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/12 ,  G06F12/00 ,  G06F15/00 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.

公开(公告)号：US09898412B2

公开(公告)日：2018-02-20

申请号：US15257593

申请日：2016-09-06

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ravishankar Rao ,  Karthikeyan Avudaiyappan

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/12 ,  G06F12/00 ,  G06F15/00 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/0864 ,  G06F9/30058 ,  G06F9/3802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452

Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.

公开(公告)号：US10140138B2

公开(公告)日：2018-11-27

申请号：US14216493

申请日：2014-03-17

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ankur Groen ,  Erika Gunadi ,  Mandeep Singh ,  Ravishankar Rao

IPC: G06F9/38 ,  G06F9/44 ,  G06F9/455 ,  G06F12/0875 ,  G06F12/1027 ,  G06F9/30 ,  G06F12/1036 ,  G06F9/32 ,  G06F12/109

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

公开(公告)号：US20180165206A1

公开(公告)日：2018-06-14

申请号：US15862496

申请日：2018-01-04

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ravishankar Rao ,  Karthikeyan Avudaiyappan

IPC: G06F12/0864 ,  G06F12/0897 ,  G06F12/0875 ,  G06F9/30 ,  G06F12/0862 ,  G06F12/0811 ,  G06F9/38

CPC classification number: G06F12/0864 ,  G06F9/30058 ,  G06F9/3802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452

Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.

公开(公告)号：US09904625B2

公开(公告)日：2018-02-27

申请号：US14215633

申请日：2014-03-17

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ravishankar Rao ,  Karthikeyan Avudaiyappan

IPC: G06F13/00 ,  G06F3/00 ,  G06F13/12 ,  G06F12/00 ,  G06F15/00 ,  G06F12/0864 ,  G06F12/0862 ,  G06F12/0811 ,  G06F9/30 ,  G06F9/38 ,  G06F12/0875 ,  G06F12/0897

CPC classification number: G06F12/0864 ,  G06F9/30058 ,  G06F9/3802 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/0897 ,  G06F2212/452

Abstract: A method for predicting a way of a set associative shadow cache is disclosed. As a part of a method, a request to fetch a first far taken branch instruction of a first cache line from an instruction cache is received, and responsive to a hit in the instruction cache, a predicted way is selected from a way array using a way that corresponds to the hit in the instruction cache. A second cache line is selected from a shadow cache using the predicted way and the first cache line and the second cache line are forwarded in the same clock cycle.

公开(公告)号：US20190056964A1

公开(公告)日：2019-02-21

申请号：US16166010

申请日：2018-10-19

Applicant: Intel Corporation

Inventor： Mohammad Abdallah ,  Ankur Groen ,  Erika Gunadi ,  Mandeep Singh ,  Ravishankar Rao

IPC: G06F9/455 ,  G06F12/109 ,  G06F12/1036 ,  G06F12/1027 ,  G06F12/0875 ,  G06F9/30 ,  G06F9/38 ,  G06F9/32

Abstract: Methods for supporting wide and efficient front-end operation with guest architecture emulation are disclosed. As a part of a method for supporting wide and efficient front-end operation, upon receiving a request to fetch a first far taken branch instruction, a cache line that includes the first far taken branch instruction, a next cache line and a cache line located at the target of the first far taken branch instruction is read. Based on information that is accessed from a data table, the cache line and either the next cache line or the cache line located at the target is fetched in a single cycle.

公开(公告)号：US09606935B2

公开(公告)日：2017-03-28

申请号：US14182618

申请日：2014-02-18

Applicant: Intel Corporation

Inventor： Ravishankar Rao ,  Nishit Shah

IPC: G06F3/00 ,  G06F12/0897 ,  G06F12/122 ,  G06F12/128 ,  G06F12/0811 ,  G06F12/1027

CPC classification number: G06F12/127 ,  G06F12/0811 ,  G06F12/0875 ,  G06F12/0897 ,  G06F12/1027 ,  G06F12/122 ,  G06F12/128 ,  G06F2212/1016 ,  G06F2212/452 ,  G06F2212/69

Abstract: A method for preventing non-temporal entries from entering small critical structures is disclosed. The method comprises transferring a first entry from a higher level memory structure to an intermediate buffer. It further comprises determining a second entry to be evicted from the intermediate buffer and a corresponding value associated with the second entry. Subsequently, responsive to a determination that the second entry is frequently accessed, the method comprises installing the second entry into a lower level memory structure. Finally, the method comprises installing the first entry into a slot previously occupied by the second entry in the intermediate buffer.