Invention Grant
- Patent Title: Method and apparatus for page-level monitoring
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Application No.: US14039195Application Date: 2013-09-27
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Publication No.: US09891936B2Publication Date: 2018-02-13
- Inventor: Jiwei Oliver Lu , Koichi Yamada , James D. Beany , Palaniverlrajan Shanmugavelayutham , Bo Zhang
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: INTEL CORPORATION
- Current Assignee: INTEL CORPORATION
- Current Assignee Address: US CA Santa Clara
- Agency: Nicholson De Vos Webster & Elliott LLP
- Main IPC: G06F12/00
- IPC: G06F12/00 ; G06F9/455 ; G06F12/10 ; G06F12/1027

Abstract:
An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.
Public/Granted literature
- US20150095590A1 METHOD AND APPARATUS FOR PAGE-LEVEL MONITORING Public/Granted day:2015-04-02
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