公开(公告)号：US09891936B2

公开(公告)日：2018-02-13

申请号：US14039195

申请日：2013-09-27

Applicant: Intel Corporation

Inventor： Jiwei Oliver Lu ,  Koichi Yamada ,  James D. Beany ,  Palaniverlrajan Shanmugavelayutham ,  Bo Zhang

IPC: G06F12/00 ,  G06F9/455 ,  G06F12/10 ,  G06F12/1027

CPC classification number: G06F9/4552 ,  G06F12/10 ,  G06F12/1027 ,  G06F2212/682 ,  G06F2212/683

Abstract: An apparatus and method for page level monitoring are described. For example, one embodiment of a method for monitoring memory pages comprises storing information related to each of a plurality of memory pages including an address identifying a location for a monitor variable for each of the plurality of memory pages in a data structure directly accessible only by a software layer operating at or above a first privilege level; detecting virtual-to-physical page mapping consistency changes or other page modifications to a particular memory page for which information is maintained in the data structure; responsively updating the monitor variable to reflect the consistency changes or page modifications; checking a first monitor variable associated with a first memory page prior to execution of first program code; and refraining from executing the first program code if the first monitor variable indicates consistency changes or page modifications to the first memory page.

公开(公告)号：US10387159B2

公开(公告)日：2019-08-20

申请号：US14614264

申请日：2015-02-04

Applicant: Intel Corporation

Inventor： Jason M Agron ,  Polychronis Xekalakis ,  Paul Caprioli ,  Jiwei Oliver Lu ,  Koichi Yamada

IPC: G06F8/52 ,  G06F9/38 ,  G06F11/34 ,  G06F11/36 ,  G06F9/455

Abstract: Methods and apparatuses relate to emulating architectural performance monitoring in a binary translation system. In one embodiment, a processor includes an architectural performance counter to maintain an architectural value associated with instruction execution, a register to store the architectural value of the architectural performance counter, binary translation logic to embed an architectural value from the architectural performance counter into a stream of translated instructions having a transactional code region and to store the architectural value into the register, and an execution unit to execute the transactional code region of the stream of translated instructions. The binary translation logic is configured to add the architectural value from the register to the architectural performance counter upon completion of the transactional code region of the stream of translated instructions. In one embodiment, a binary translation system overcomes software incompatibilities by using microarchitectural support to transparently and accurately emulate architectural performance counter behavior.