- 专利标题: Behavioral simulation model for clock-data recovery phase-locked loop
-
申请号: US14723153申请日: 2015-05-27
-
公开(公告)号: US09898561B2公开(公告)日: 2018-02-20
- 发明人: Bo Zhou , Ajay Nagarandal
- 申请人: Altera Corporation
- 申请人地址: US CA San Jose
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 当前专利权人地址: US CA San Jose
- 代理机构: Fletcher Yoder, P.C.
- 主分类号: H04L7/00
- IPC分类号: H04L7/00 ; G06F17/50 ; H03L7/08 ; H04L7/033
摘要:
Method and non-transitory computer-readable medium storing instructions for simulating a phase-locked loop measures a first phase of a data signal and a second phase of a reference clock signal in a phase-locked loop to be simulated, filters the first phase of the data signal by a threshold function of a lock detection module of the phase-locked loop to be simulated, and adjusts the second phase of the reference clock signal to align with the filtered first phase of the data signal.
公开/授权文献
信息查询