- 专利标题: Interconnect structures for wafer level package and methods of forming same
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申请号: US15591403申请日: 2017-05-10
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公开(公告)号: US09899288B2公开(公告)日: 2018-02-20
- 发明人: Chih-Hao Chang , Tsung-Hsien Chiang , Guan-Yu Chen , Wei Sen Chang , Tin-Hao Kuo , Hao-Yi Tsai , Chen-Hua Yu
- 申请人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 申请人地址: TW Hsin-Chu
- 专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人: Taiwan Semiconductor Manufacturing Company, Ltd.
- 当前专利权人地址: TW Hsin-Chu
- 代理机构: Slater Matsil, LLP
- 主分类号: H01L23/498
- IPC分类号: H01L23/498 ; H01L23/31 ; H01L23/538 ; H01L23/29 ; H01L25/065
摘要:
A device package is provided. The device package includes a first die and a second die. A top surface of the first die is offset from a top surface of the second die in a direction that is parallel to a sidewall of the first die. A molding compound extends along sidewalls of the first die and the second die, where at least a portion of a top surface of the molding compound includes an inclined surface. A polymer layer contacts the top surface of the molding compound, the top surface of the first die, and the top surface of the second die. A top surface of the polymer layer is substantially level. A first conductive feature is in the polymer layer, where the first conductive feature is electrically connected to the first die.
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