公开(公告)号：US11251303B2

公开(公告)日：2022-02-15

申请号：US16986043

申请日：2020-08-05

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/165 ,  H01L21/76 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16

摘要： A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

公开(公告)号：US11239365B2

公开(公告)日：2022-02-01

申请号：US16726405

申请日：2019-12-24

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shao-Ming Yu ,  Chang-Yun Chang ,  Chih-Hao Chang ,  Hsin-Chih Chen ,  Kai-Tai Chang ,  Ming-Feng Shieh ,  Kuei-Liang Lu ,  Yi-Tang Lin

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/67 ,  H01L27/088

摘要： A semiconductor structure includes an isolation feature formed in the semiconductor substrate and a first fin-type active region. The first fin-type active region extends in a first direction. A dummy gate stack is disposed on an end region of the first fin-type active region. The dummy gate stack may overlie an isolation structure. In an embodiment, any recess such as formed for a source/drain region in the first fin-type active region will be displaced from the isolation region by the distance the dummy gate stack overlaps the first fin-type active region.

公开(公告)号：US10693003B2

公开(公告)日：2020-06-23

申请号：US15600311

申请日：2017-05-19

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chang ,  Jeff J. Xu ,  Chien-Hsun Wang ,  Chih Chieh Yeh ,  Chih-Hsiang Chang

IPC分类号： H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L29/161 ,  H01L21/18 ,  H01L21/02 ,  H01L29/10

摘要： An embodiment of a method for forming a transistor that includes providing a semiconductor substrate having a source/drain region is provided where a first SiGe layer is formed over the source/drain region. A thermal oxidation is performed to convert a top portion of the first SiGe layer to an oxide layer and a bottom portion of the first SiGe layer to a second SiGe layer. A thermal diffusion process is performed after the thermal oxidation is performed to form a SiGe area from the second SiGe layer. The SiGe area has a higher Ge concentration than the first SiGe layer.

公开(公告)号：US10515956B2

公开(公告)日：2019-12-24

申请号：US16042064

申请日：2018-07-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

IPC分类号： H01L27/088 ,  H01L29/66 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/06 ,  H01L29/06 ,  H01L27/02 ,  H01L29/78

摘要： Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

公开(公告)号：US20190273150A1

公开(公告)日：2019-09-05

申请号：US16419292

申请日：2019-05-22

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Ting Li ,  Bi-Fen Wu ,  Jen-Hsiang Lu ,  Chih-Hao Chang

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/28 ,  H01L29/417 ,  H01L27/088 ,  H01L29/06

摘要： A method includes forming a fin extending above an isolation region. A sacrificial gate stack having a first sidewall and a second sidewall opposite the first sidewall is formed over the fin. A first spacer is formed on the first sidewall of the sacrificial gate stack. A second spacer is formed on the second sidewall of the sacrificial gate stack. A patterned mask having an opening therein is formed over the sacrificial gate stack, the first spacer and the second spacer. The patterned mask extends along a top surface and a sidewall of the first spacer. The second spacer is exposed through the opening in the patterned mask. The fin is patterned using the patterned mask, the sacrificial gate stack, the first spacer and the second spacer as a combined mask to form a recess in the fin. A source/drain region is epitaxially grown in the recess.

公开(公告)号：US09564529B2

公开(公告)日：2017-02-07

申请号：US14844247

申请日：2015-09-03

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Tsung-Lin Lee ,  Chih-Hao Chang ,  Chih-Hsin Ko ,  Feng Yuan ,  Jeff J. Xu

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L21/76 ,  H01L29/165 ,  H01L21/02 ,  H01L21/306 ,  H01L21/31 ,  H01L21/311 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L21/30604 ,  H01L21/31 ,  H01L21/31116 ,  H01L21/76 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0856 ,  H01L29/0873 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

摘要： A field effect transistor includes a substrate comprising a fin structure. The field effect transistor further includes an isolation structure in the substrate. The field effect transistor further includes a source/drain (S/D) recess cavity below a top surface of the substrate. The S/D recess cavity is between the fin structure and the isolation structure. The field effect transistor further includes a strained structure in the S/D recess cavity. The strain structure includes a lower portion. The lower portion includes a first strained layer, wherein the first strained layer is in direct contact with the isolation structure, and a dielectric layer, wherein the dielectric layer is in direct contact with the substrate, and the first strained layer is in direct contact with the dielectric layer. The strained structure further includes an upper portion comprising a second strained layer overlying the first strained layer.

摘要翻译： 场效应晶体管包括包括鳍结构的衬底。 场效应晶体管还包括衬底中的隔离结构。 场效应晶体管还包括在衬底的顶表面下方的源/漏（S / D）凹槽。 S / D凹陷腔位于翅片结构和隔离结构之间。 场效应晶体管还包括S / D凹陷腔中的应变结构。 应变结构包括下部。 所述下部包括第一应变层，其中所述第一应变层与所述隔离结构直接接触;以及介电层，其中所述电介质层与所述基板直接接触，并且所述第一应变层与所述第一应变层直接接触 电介质层。 应变结构还包括上部，其包括覆盖在第一应变层上的第二应变层。

公开(公告)号：US20160064381A1

公开(公告)日：2016-03-03

申请号：US14937529

申请日：2015-11-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chih-Hao Chang ,  Jeff J. Xu

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L27/0886 ,  H01L27/12 ,  H01L29/0642 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7851

摘要： A FinFET device and method for fabricating a FinFET device is disclosed. An exemplary device includes a fin structure formed over a semiconductor substrate. The fin structure includes a source region and a drain region that include a first material layer disposed over the semiconductor substrate, a second material layer disposed over the first material layer, and a third material layer disposed over the second material layer. The first, second, and third material layers are different from each other. The fin structure also has a channel defined between the source and drain regions. The channel includes the first material layer disposed over the semiconductor substrate and the second semiconductor material layer disposed over the first material layer.

摘要翻译： 公开了一种用于制造FinFET器件的FinFET器件和方法。 示例性器件包括在半导体衬底上形成的鳍结构。 鳍结构包括源极区和漏极区，其包括设置在半导体衬底上的第一材料层，设置在第一材料层上的第二材料层和设置在第二材料层上的第三材料层。 第一，第二和第三材料层彼此不同。 翅片结构还具有在源区和漏区之间限定的通道。 通道包括设置在半导体衬底上的第一材料层和设置在第一材料层上的第二半导体材料层。

公开(公告)号：US09219152B2

公开(公告)日：2015-12-22

申请号：US13658348

申请日：2012-10-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Zhiqiang Wu ,  Jeffrey Junhao Xu ,  Chih-Hao Chang ,  Wen-Hsing Hsieh

IPC分类号： H01L29/78 ,  H01L21/336 ,  H01L29/165 ,  H01L29/66

CPC分类号： H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7848

摘要： A semiconductor device, such as a PMOS or NMOS device, having localized stressors is provided. Recesses are formed on opposing sides of a gate electrode. A stress-inducing region is formed along a bottom of the recess, and a stressed layer is formed over the stress-inducing region. By having a stress-inducing region with a larger lattice structure than the stressed layer, a tensile strain may be created in a channel region of the semiconductor device and may be suitable for an NMOS device. By having a stress-inducing region with a smaller lattice structure than the stressed layer, a compressive strain may be created in the channel region of the semiconductor device and may be suitable for a PMOS device. Embodiments may be applied to various types of substrates and semiconductor devices, such as planar transistors and finFETs.

摘要翻译： 提供了具有局部应力源的半导体器件，例如PMOS或NMOS器件。 凹槽形成在栅电极的相对侧上。 沿着凹部的底部形成应力诱导区域，在应力诱导区域上形成应力层。 通过具有比应力层更大的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生拉伸应变，并且可以适用于NMOS器件。 通过具有比应力层更小的晶格结构的应力诱导区域，可以在半导体器件的沟道区域中产生压应变，并且可以适用于PMOS器件。 实施例可以应用于各种类型的基板和半导体器件，例如平面晶体管和finFET。

公开(公告)号：US20150017768A1

公开(公告)日：2015-01-15

申请号：US14269748

申请日：2014-05-05

申请人： Taiwan Semiconductor Manufacturing Company Ltd.

发明人： Clement Hsingjen Wann ,  Chih-Hao Chang ,  Shou Zen Chang ,  Chih-Hsin Ko ,  Yasutoshi Okuno ,  Andrew Joseph Kelly

IPC分类号： H01L21/8238 ,  H01L29/66

CPC分类号： H01L21/823814 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823828 ,  H01L21/823871 ,  H01L23/485 ,  H01L29/6656 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a semiconductor substrate including an active region including a plurality of device regions. The semiconductor device further includes a first device disposed in a first device region of the plurality of device regions, the first device including a first gate structure, first gate spacers disposed on sidewalls of the first gate structure, and first source and drain features. The semiconductor device further includes a second device disposed in a second device region of the plurality of device regions, the second device including a second gate structure, second gate spacers disposed on sidewalls of the second gate structure, and second source and drain features. The second and first source and drain features having a source and drain feature and a contact feature in common. The common contact feature being a self-aligned contact.

摘要翻译： 公开了一种用于制造半导体器件的半导体器件和方法。 示例性半导体器件包括包括包括多个器件区域的有源区的半导体衬底。 半导体器件还包括设置在多个器件区域的第一器件区域中的第一器件，第一器件包括第一栅极结构，设置在第一栅极结构的侧壁上的第一栅极间隔区以及第一源极和漏极特征。 半导体器件还包括设置在多个器件区域的第二器件区域中的第二器件，第二器件包括第二栅极结构，设置在第二栅极结构的侧壁上的第二栅极间隔区以及第二源极和漏极特征。 第二和第一源极和漏极特征具有源极和漏极特征以及共同的接触特征。 常见的接触特征是自对准接触。

公开(公告)号：US20140147978A1

公开(公告)日：2014-05-29

申请号：US14166585

申请日：2014-01-28

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Chung-Hsien Chen ,  Ting-Chu Ko ,  Chih-Hao Chang ,  Chih-Sheng Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann

IPC分类号： H01L21/8238 ,  H01L21/02

CPC分类号： H01L21/02664 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/28518 ,  H01L21/76814 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7845 ,  H01L29/7848

摘要： A semiconductor device comprises a substrate comprising a major surface; a p-type Field Effect Transistor (pFET) comprising: a P-gate stack over the major surface, a P-strained region in the substrate adjacent to one side of the P-gate stack, wherein a lattice constant of the P-strained region is different from a lattice constant of the substrate, wherein the P-strained region has a first top surface higher than the major surface; and a P-silicide region on the P-strained region; and an n-type Field Effect Transistor (nFET) comprising: an N-gate stack over the major surface, an N-strained region in the substrate adjacent to one side of the N-gate stack, wherein a lattice constant of the N-strained region is different from a lattice constant of the substrate, wherein the N-strained region has a second top surface lower than the major surface and a N-silicide region on the N-strained region.

摘要翻译： 一种半导体器件包括：包括主表面的衬底; p型场效应晶体管（pFET），包括：主表面上的P栅极堆叠，与所述P栅极堆叠的一侧相邻的所述衬底中的P-应变区，其中所述P-应变的晶格常数 区域不同于衬底的晶格常数，其中P应变区具有高于主表面的第一顶表面; 和P-应变区上的P-硅化物区域; 和n型场效应晶体管（nFET），其包括：主表面上的N-栅极堆叠，与所述N-栅极堆叠的一侧相邻的所述衬底中的N-应变区，其中， 应变区域与衬底的晶格常数不同，其中N-应变区域具有低于主表面的第二顶表面和N-应变区域上的N-硅化物区域。