Invention Grant
- Patent Title: Method for fabricating semiconductor device having a patterned metal layer embedded in an interlayer dielectric layer
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Application No.: US15257921Application Date: 2016-09-07
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Publication No.: US09899322B2Publication Date: 2018-02-20
- Inventor: Ching-Ling Lin , Chih-Sen Huang , Ching-Wen Hung , Jia-Rong Wu , Tsung-Hung Chang , Yi-Hui Lee , Yi-Wei Chen
- Applicant: UNITED MICROELECTRONICS CORP.
- Applicant Address: TW Hsin-Chu
- Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee: UNITED MICROELECTRONICS CORP.
- Current Assignee Address: TW Hsin-Chu
- Agent Winston Hsu
- Priority: CN201410430805 20140828
- Main IPC: H01L21/338
- IPC: H01L21/338 ; H01L23/528 ; H01L21/768 ; H01L27/06 ; H01L21/8234 ; H01L23/532

Abstract:
A method for fabricating semiconductor device is disclosed. First, a substrate is provided, in which the substrate includes a first metal gate and a second metal gate thereon, a first hard mask on the first metal gate and a second hard mask on the second metal gate, and a first interlayer dielectric (ILD) layer around the first metal gate and the second metal gate. Next, the first hard mask and the second hard mask are used as mask to remove part of the first ILD layer for forming a recess, and a patterned metal layer is formed in the recess, in which the top surface of the patterned metal layer is lower than the top surfaces of the first hard mask and the second hard mask.
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