Invention Grant
- Patent Title: Conductivity improvements for III-V semiconductor devices
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Application No.: US14597128Application Date: 2015-01-14
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Publication No.: US09899505B2Publication Date: 2018-02-20
- Inventor: Marko Radosavljevic , Prashant Majhi , Jack T. Kavalieros , Niti Goel , Wilman Tsai , Niloy Mukherjee , Yong Ju Lee , Gilbert Dewey , Willy Rachmady
- Applicant: INTEL CORPORATION
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Schwabe, Williamson & Wyatt P.C.
- Main IPC: H01L29/66
- IPC: H01L29/66 ; H01L29/778 ; H01L21/225 ; H01L29/20 ; H01L29/423 ; H01L29/47

Abstract:
Conductivity improvements in III-V semiconductor devices are described. A first improvement includes a barrier layer that is not coextensively planar with a channel layer. A second improvement includes an anneal of a metal/Si, Ge or SiliconGermanium/III-V stack to form a metal-Silicon, metal-Germanium or metal-SiliconGermanium layer over a Si and/or Germanium doped III-V layer. Then, removing the metal layer and forming a source/drain electrode on the metal-Silicon, metal-Germanium or metal-SiliconGermanium layer. A third improvement includes forming a layer of a Group IV and/or Group VI element over a III-V channel layer, and, annealing to dope the III-V channel layer with Group IV and/or Group VI species. A fourth improvement includes a passivation and/or dipole layer formed over an access region of a III-V device.
Public/Granted literature
- US20150123171A1 CONDUCTIVITY IMPROVEMENTS FOR III-V SEMICONDUCTOR DEVICES Public/Granted day:2015-05-07
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