公开(公告)号：US12183831B2

公开(公告)日：2024-12-31

申请号：US16638301

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Van H. Le ,  Abhishek A. Sharma ,  Benjamin Chu-Kung ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Miriam R. Reshotko ,  Shriram Shivaraman ,  Li Huey Tan ,  Tristan A. Tronic ,  Jack T. Kavalieros

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/40 ,  H01L29/417

Abstract: Embodiments herein describe techniques for a semiconductor device, which may include a substrate, and a U-shaped channel above the substrate. The U-shaped channel may include a channel bottom, a first channel wall and a second channel wall parallel to each other, a source area, and a drain area. A gate dielectric layer may be above the substrate and in contact with the channel bottom. A gate electrode may be above the substrate and in contact with the gate dielectric layer. A source electrode may be coupled to the source area, and a drain electrode may be coupled to the drain area. Other embodiments may be described and/or claimed.

公开(公告)号：US12120865B2

公开(公告)日：2024-10-15

申请号：US17132981

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

CPC classification number: H10B12/30 ,  H01L21/6835 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B53/30 ,  H01L2221/68363

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US11929435B2

公开(公告)日：2024-03-12

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/2003 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.

公开(公告)号：US11923290B2

公开(公告)日：2024-03-05

申请号：US16913859

申请日：2020-06-26

Applicant: Intel Corporation

Inventor： Siddharth Chouksey ,  Gilbert Dewey ,  Nazila Haratipour ,  Mengcheng Lu ,  Jitendra Kumar Jha ,  Jack T. Kavalieros ,  Matthew V. Metz ,  Scott B Clendenning ,  Eric Charles Mattson

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L29/78

CPC classification number: H01L23/5226 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/53266 ,  H01L29/785 ,  H01L2029/7858

Abstract: Embodiments disclosed herein include semiconductor devices with source/drain interconnects that include a barrier layer. In an embodiment the semiconductor device comprises a source region and a drain region. In an embodiment, a semiconductor channel is between the source region and the drain region, and a gate electrode is over the semiconductor channel. In an embodiment, the semiconductor device further comprises interconnects to the source region and the drain region. In an embodiment, the interconnects comprise a barrier layer, a metal layer, and a fill metal.

公开(公告)号：US11916118B2

公开(公告)日：2024-02-27

申请号：US18130824

申请日：2023-04-04

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey

IPC: H01L29/417

CPC classification number: H01L29/41741 ,  H01L29/41775

Abstract: A device is disclosed. The device includes a first epitaxial region, a second epitaxial region, a first gate region between the first epitaxial region and a second epitaxial region, a first dielectric structure underneath the first epitaxial region, a second dielectric structure underneath the second epitaxial region, a third epitaxial region underneath the first epitaxial region, a fourth epitaxial region underneath the second epitaxial region, and a second gate region between the third epitaxial region and a fourth epitaxial region and below the first gate region. The device also includes, a conductor via extending from the first epitaxial region, through the first dielectric structure and the third epitaxial region, the conductor via narrower at an end of the conductor via that contacts the first epitaxial region than at an opposite end.

公开(公告)号：US11777013B2

公开(公告)日：2023-10-03

申请号：US16457626

申请日：2019-06-28

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Willy Rachmady ,  Van H. Le ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Matthew Metz

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L29/45 ,  H01L29/786 ,  H01L29/417

CPC classification number: H01L29/66742 ,  H01L21/0262 ,  H01L21/02603 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/78618 ,  H01L29/78696

Abstract: Embodiments herein describe techniques for a three dimensional transistor above a substrate. A three dimensional transistor includes a channel structure, where the channel structure includes a channel material and has a source area, a drain area, and a channel area between the source area and the drain area. A source electrode is coupled to the source area, a drain electrode is coupled to the drain area, and a gate electrode is around the channel area. An electrode selected from the source electrode, the drain electrode, or the gate electrode is in contact with the channel material on a sidewall of an opening in an inter-level dielectric layer or a surface of the electrode. The electrode is further in contact with the channel structure including the source area, the drain area, or the channel area. Other embodiments may be described and/or claimed.

公开(公告)号：US11764263B2

公开(公告)日：2023-09-19

申请号：US16240156

申请日：2019-01-04

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Anh Phan ,  Aaron Lilak ,  Willy Rachmady ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Richard Schenker ,  Hui Jae Yoo ,  Patrick Morrow

IPC: H01L29/06 ,  H01L27/088 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423

CPC classification number: H01L29/068 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/785 ,  H01L2029/7858

Abstract: Gate-all-around integrated circuit structures having depopulated channel structures, and methods of fabricating gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches, are described. For example, an integrated circuit structure includes a vertical arrangement of nanowires. All nanowires of the vertical arrangement of nanowires are oxide nanowires. A gate stack is over the vertical arrangement of nanowires, around each of the oxide nanowires. The gate stack includes a conductive gate electrode.

公开(公告)号：US11742346B2

公开(公告)日：2023-08-29

申请号：US16024058

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： Aaron D. Lilak ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Christopher Jezewski ,  Ehren Mannebach ,  Rishabh Mehandru ,  Patrick Morrow ,  Anand S. Murthy ,  Anh Phan ,  Willy Rachmady

IPC: H01L27/088 ,  H01L21/768 ,  H01L21/8258 ,  H01L21/84 ,  H01L23/48 ,  H01L23/522 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/822 ,  H01L23/00

CPC classification number: H01L27/0886 ,  H01L21/76898 ,  H01L21/8258 ,  H01L21/845 ,  H01L23/481 ,  H01L23/5226 ,  H01L24/29 ,  H01L24/32 ,  H01L27/0924 ,  H01L24/94 ,  H01L2224/29188 ,  H01L2224/32145

Abstract: Stacked transistor structures having a conductive interconnect between source/drain regions of upper and lower transistors. In some embodiments, the interconnect is provided, at least in part, by highly doped epitaxial material deposited in the upper transistor's source/drain region. In such cases, the epitaxial material seeds off of an exposed portion of semiconductor material of or adjacent to the upper transistor's channel region and extends downward into a recess that exposes the lower transistor's source/drain contact structure. The epitaxial source/drain material directly contacts the lower transistor's source/drain contact structure, to provide the interconnect. In other embodiments, the epitaxial material still seeds off the exposed semiconductor material of or proximate to the channel region and extends downward into the recess, but need not contact the lower contact structure. Rather, a metal-containing contact structure passes through the epitaxial material of the upper source/drain region and contacts the lower transistor's source/drain contact structure.

公开(公告)号：US20230193473A1

公开(公告)日：2023-06-22

申请号：US17559897

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Debaleena Nandi ,  Gilbert Dewey ,  Tahir Ghani ,  Nazila Haratipour ,  Mauro J. Kobrinsky ,  Anand Murthy

IPC: C23C28/00 ,  H01L23/538

CPC classification number: C23C28/34 ,  C23C28/32 ,  C23C28/36 ,  H01L23/5383

Abstract: The formation of titanium contacts to silicon germanium (SiGe) comprises the formation of a titanium silicide layer in which the silicon for the titanium silicide layer is provided by flowing silane (disilane, trisilane, etc.) over a titanium layer at an elevated temperature. The titanium silicide layer can help limit the amount of titanium and germanium interdiffusion that can occur across the titanium silicide-silicon germanium interface, which can reduce (or eliminate) the formation of voids in the SiGe layer during subsequent anneal and other high-temperature processes. The surface of the SiGe layer upon which the titanium layer is formed can also be preamorphized via boron and germanium implantation to further improve the robustness of the SiGe layer against microvoid development. The resulting titanium contacts are thermally stable in that their resistance remains substantially unchanged after being subjected to downstream annealing and high-temperature processing processes.

公开(公告)号：US11664373B2

公开(公告)日：2023-05-30

申请号：US17555296

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Aaron Lilak ,  Patrick Morrow ,  Gilbert Dewey ,  Willy Rachmady ,  Rishabh Mehandru

IPC: H01L27/06 ,  H01L21/82 ,  H01L29/78 ,  H01L29/06 ,  H01L27/02 ,  H01L23/522 ,  H01L21/8234 ,  H01L21/822

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/5226 ,  H01L27/0207 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0684 ,  H01L29/7851

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a lower device layer that includes a first transistor structure, an upper device layer above the lower device layer including a second transistor structure, and an isolation wall that extends between the upper device layer and the lower device layer. The isolation wall may be in contact with an edge of a first gate structure of the first transistor structure and an edge of a second gate structure of the second transistor structure, and may have a first width to the edge of the first gate structure at the lower device layer, and a second width to the edge of the second gate structure at the upper device layer. The first width may be different from the second width. Other embodiments may be described and/or claimed.