Invention Grant
- Patent Title: Semiconductor device and method for manufacturing semiconductor device
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Application No.: US15408719Application Date: 2017-01-18
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Publication No.: US09905657B2Publication Date: 2018-02-27
- Inventor: Yuta Endo , Hideomi Suzawa , Kazuya Hanaoka , Shinya Sasagawa , Satoru Okamoto
- Applicant: Semiconductor Energy Laboratory Co., Ltd.
- Applicant Address: JP Atsugi-shi, Kanagawa-ken
- Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
- Current Assignee Address: JP Atsugi-shi, Kanagawa-ken
- Agency: Fish & Richardson P.C.
- Priority: JP2016-009178 20160120
- Main IPC: H01L29/40
- IPC: H01L29/40 ; H01L29/786 ; H01L29/66 ; H01L29/423 ; H01L29/49 ; H01L27/12 ; H01L27/146

Abstract:
A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.
Public/Granted literature
- US20170207347A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Public/Granted day:2017-07-20
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