Invention Grant
- Patent Title: Techniques for entry to a lower power state for a memory device
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Application No.: US15344809Application Date: 2016-11-07
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Publication No.: US09916104B2Publication Date: 2018-03-13
- Inventor: Sowmiya Jayachandran , Rajesh Sundaram , Robert Faber
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Compass IP Law PC
- Main IPC: G11C5/14
- IPC: G11C5/14 ; G06F3/06

Abstract:
Examples are given for techniques for entry to a lower power state for a memory device or die. The examples to include delaying transitions of the memory device or die from a first higher consuming power state to a second relatively lower power state using one or more programmable counters maintained at or with the memory device.
Public/Granted literature
- US20170115916A1 TECHNIQUES FOR ENTRY TO A LOWER POWER STATE FOR A MEMORY DEVICE Public/Granted day:2017-04-27
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