公开(公告)号：US11687404B2

公开(公告)日：2023-06-27

申请号：US17530281

申请日：2021-11-18

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Wei Wu ,  Rajesh Sundaram ,  Shigeki Tomishima

IPC: G06F11/00 ,  G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1044 ,  G06F11/0772 ,  G06F11/0793

Abstract: Technologies for preserving error correction capability in compute-in-memory operations in a memory include memory media and a media access circuitry coupled with the memory media. The media access circuitry is to detect an error code adjustment state indicative of a failure in the initiated error correction. The media access circuitry is to adjust a voltage to the memory media to eliminate the error code correction adjustment state. Once eliminated, the media access circuitry is to perform the error correction on the read data.

公开(公告)号：US11620358B2

公开(公告)日：2023-04-04

申请号：US16411730

申请日：2019-05-14

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Rajesh Sundaram ,  Richard Coulson ,  Bruce Querbach ,  Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan

IPC: G06F17/16 ,  G06F9/30

Abstract: Technologies for performing in-memory macro operations include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory macro operation indicative of a set of multiple in-memory operations. The media access circuitry is also to perform, in response to the request, the in-memory macro operation on data present in the memory media.

公开(公告)号：US11604834B2

公开(公告)日：2023-03-14

申请号：US16870003

申请日：2020-05-08

Applicant: Intel Corporation

Inventor： Mariano Tepper ,  Dipanjan Sengupta ,  Sourabh Dongaonkar ,  Chetan Chauhan ,  Jawad Khan ,  Theodore Willke ,  Richard Coulson ,  Rajesh Sundaram

IPC: G06F16/903 ,  G06F17/16 ,  G06K9/62

Abstract: Technologies for performing stochastic similarity searches in an online clustering space include a device having a column addressable memory and circuitry. The circuitry is configured to determine a Hamming distance from a binary dimensionally expanded vector to each cluster of a set of clusters of binary dimensionally expanded vectors in the memory, identify the cluster having the smallest Hamming distance from the binary dimensionally expanded vector, determine whether the identified cluster satisfies a target size, and add or delete, in response to a determination that the identified cluster does not satisfy the target size, the binary dimensionally expanded vector to or from the identified cluster.

公开(公告)号：US11327881B2

公开(公告)日：2022-05-10

申请号：US15930889

申请日：2020-05-13

Applicant: Intel Corporation

Inventor： Chetan Chauhan ,  Sourabh Dongaonkar ,  Rajesh Sundaram ,  Jawad Khan ,  Sandeep Guliani ,  Dipanjan Sengupta ,  Mariano Tepper

IPC: G06F12/02 ,  G06F16/27

Abstract: Technologies for media management for providing column data layouts for clustered data include a device having a column-addressable memory and circuitry connected to the memory. The circuitry is configured to store a data cluster of a logical matrix in the column-addressable memory with a column-based format and to read a logical column of the data cluster from the column-addressable memory with a column read operation. Reading the logical column may include reading logical column data diagonally from the column-address memory, including reading from the data cluster and a duplicate copy of the data cluster. Reading the logical column may include reading from multiple complementary logical columns. Reading the logical column may include reading logical column data diagonally with a modulo counter. The column data may bread from a partition of the column-address memory selected based on the logical column number. Other embodiments are described and claimed.

公开(公告)号：US11188264B2

公开(公告)日：2021-11-30

申请号：US16780632

申请日：2020-02-03

Applicant: Intel Corporation

Inventor： Shekoufeh Qawami ,  Philip Hillier ,  Benjamin Graniello ,  Rajesh Sundaram

IPC: G06F3/06

Abstract: A memory system includes a nonvolatile (NV) memory device with asymmetry between intrinsic read operation delay and intrinsic write operation delay. The system can select to perform memory access operations with the NV memory device with the asymmetry, in which case write operations have a lower delay than read operations. The system can alternatively select to perform memory access operations with the NV memory device where a configured write operation delay that matches the read operation delay.

公开(公告)号：US10936418B2

公开(公告)日：2021-03-02

申请号：US16444480

申请日：2019-06-18

Applicant: Intel Corporation

Inventor： Kiran Pangal ,  Prashant S. Damle ,  Rajesh Sundaram ,  Shekoufeh Qawami ,  Julie M. Walker ,  Doyle Rivers

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/05 ,  H03M13/27 ,  H03M13/00 ,  G06F3/06 ,  H03M13/15 ,  H03M13/19

Abstract: Uncorrectable memory errors may be reduced by determining a logical array address for a set of memory arrays and transforming the logical array address to at least two unique array addresses based, at least in part, on logical locations of at least two memory arrays within the set of memory arrays. The at least two memory arrays are then accessed using the at least two unique array addresses, respectively.

公开(公告)号：US10541009B2

公开(公告)日：2020-01-21

申请号：US15857349

申请日：2017-12-28

Applicant: Intel Corporation

Inventor： David J. Zimmerman ,  Robert M. Ellis ,  Rajesh Sundaram

IPC: G06F3/06 ,  G11C7/10

Abstract: Devices, systems, and methods having increased efficiency selective writing to memory are disclosed and described. A memory controller, upon receiving a dirty data segment, performs a read-modify-write to retrieve a corresponding data line from memory, saves a copy of the data line, merges the dirty data segment into the appropriate location in the data line to create a modified data line, and generates a write mask from the modified data line and the copy of the data line.

公开(公告)号：US10534747B2

公开(公告)日：2020-01-14

申请号：US16368983

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram ,  Jawad B. Khan

IPC: G06F7/38 ,  H03K19/173 ,  G06F15/78 ,  G06F15/80 ,  G06F17/16

Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.

公开(公告)号：US20190272173A1

公开(公告)日：2019-09-05

申请号：US16419483

申请日：2019-05-22

Applicant: Intel Corporation

Inventor： Bruce Querbach ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F9/30 ,  G06F9/50

Abstract: Technologies for providing adaptive memory media management include media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform at least one memory access operation to be managed by the media access circuitry. The media access circuitry is further to manage the requested at least one memory access operation, including disabling a memory controller in communication with the media access circuitry from managing the memory media while the at least one requested memory access operation is performed.

公开(公告)号：US20190272121A1

公开(公告)日：2019-09-05

申请号：US16414265

申请日：2019-05-16

Applicant: Intel Corporation

Inventor： Jawad B. Khan ,  Shigeki Tomishima ,  Srikanth Srinivasan ,  Chetan Chauhan ,  Rajesh Sundaram

IPC: G06F3/06 ,  H03M13/29 ,  G06F11/10 ,  G06N3/08 ,  G11C7/10

Abstract: Technologies for providing multiple tier memory media management include a memory having a media access circuitry connected to a memory media. The media access circuitry is to receive a request to perform an in-memory compute operation. Additionally, the media access circuitry is to read, in response to the request, data from a memory media region of the memory media, write the read data into a compute media region of the memory, perform, on the data in the compute media region, the in-memory compute operation, write, to the memory media region, resultant data indicative of a result of performance of the in-memory compute operation.