Invention Grant
- Patent Title: Bump-on-lead flip chip interconnection
-
Application No.: US13965356Application Date: 2013-08-13
-
Publication No.: US09922915B2Publication Date: 2018-03-20
- Inventor: Rajendra D. Pendse
- Applicant: STATS ChipPAC, Ltd.
- Applicant Address: SG Singapore
- Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee: STATS ChipPAC Pte. Ltd.
- Current Assignee Address: SG Singapore
- Agency: Patent Law Group: Atkins and Associates, P.C.
- Agent Robert D. Atkins
- Main IPC: H01L21/44
- IPC: H01L21/44 ; H01L23/48 ; H01L23/52 ; H01L23/498 ; H01L21/56 ; H01L21/768 ; H01L23/00

Abstract:
A semiconductor device has a semiconductor die with a plurality of bumps formed over the die. A substrate has a plurality of conductive traces formed on the substrate. Each trace has an interconnect site for mating to the bumps. The interconnect sites have parallel edges along a length of the conductive traces under the bumps from a plan view for increasing escape routing density. The bumps have a noncollapsible portion for attaching to a contact pad on the die and fusible portion for attaching to the interconnect site. [The fusible portion melts at a temperature which avoids damage to the substrate during reflow.] The noncollapsible portion includes lead solder, and fusible portion includes eutectic solder. The interconnect sites have a width which is less than 1.2 times a width of the conductive trace. Alternatively, the interconnect sites have a width which is less than one-half a diameter of the bump.
Public/Granted literature
- US20130328189A1 Bump-on-Lead Flip Chip Interconnection Public/Granted day:2013-12-12
Information query
IPC分类: