Invention Grant
- Patent Title: Method and apparatus for hybrid chip-level voltage scaling
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Application No.: US13771064Application Date: 2013-02-19
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Publication No.: US09933827B2Publication Date: 2018-04-03
- Inventor: Ajay Cheriyan , Rajesh Joshi , Madan Krishnappa
- Applicant: QUALCOMM Incorporated
- Applicant Address: US CA San Diego
- Assignee: QUALCOMM Incorporated
- Current Assignee: QUALCOMM Incorporated
- Current Assignee Address: US CA San Diego
- Agency: Loza & Loza, LLP/Qualcomm
- Main IPC: G06F1/32
- IPC: G06F1/32

Abstract:
Various aspects of a power management approach for a system-on-a-chip (SoC) is disclosed herein. In one aspect, the approach includes implementing a power profile for supplying power to a plurality of subsystems on a shared power bus in the SoC. The power profile includes at least one adjustable parameter for controlling the supplied power during an active use state. The approach further includes detecting a power profile change trigger; modifying the power profile based on the power profile change trigger; and adjusting the supplied power during the active use state based on the modified power profile to maintain a predetermined supplied power level.
Public/Granted literature
- US20140232188A1 METHOD AND APPARATUS FOR HYBRID CHIP-LEVEL VOLTAGE SCALING Public/Granted day:2014-08-21
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