Invention Grant
- Patent Title: Apparatus and method to provide multiple domain clock frequencies in a processor
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Application No.: US14551310Application Date: 2014-11-24
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Publication No.: US09933845B2Publication Date: 2018-04-03
- Inventor: Alexander Gendler
- Applicant: Intel Corporation
- Applicant Address: US CA Santa Clara
- Assignee: Intel Corporation
- Current Assignee: Intel Corporation
- Current Assignee Address: US CA Santa Clara
- Agency: Trop, Pruner & Hu, P.C.
- Main IPC: G06F1/32
- IPC: G06F1/32 ; G06F1/04

Abstract:
In an embodiment, a processor includes at least one core, a first domain to operate at a first clock frequency, and a second domain to operate at a second clock frequency that is lower than the first clock frequency. The processor also includes phase locked loop (PLL) logic to generate a first signal having a first frequency corresponding to the first clock frequency and to provide the first signal to the first domain. The processor also includes a first clock to produce a first squash signal that is determined based at least in part on the second clock frequency, and also first logic to generate a second signal having a second frequency corresponding to the second clock frequency by gating the first signal with the first squash signal and to provide the second signal to the second domain. Other embodiments are described and claimed.
Public/Granted literature
- US20160147249A1 Apparatus and Method to Provide Multiple Domain Clock Frequencies In A Processor Public/Granted day:2016-05-26
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