- Patent Title: Integrated circuit with transistor array and layout method thereof
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Application No.: US15161585Application Date: 2016-05-23
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Publication No.: US09964987B2Publication Date: 2018-05-08
- Inventor: Ching-Ho Chang , Jaw-Juinn Horng , Yung-Chow Peng
- Applicant: Taiwan Semiconductor Manufacturing CO., LTD.
- Applicant Address: TW Hsinchu
- Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
- Current Assignee Address: TW Hsinchu
- Main IPC: H01L27/118
- IPC: H01L27/118 ; H01L21/82 ; G05F3/26 ; H01L29/423 ; H01L27/06 ; H01L27/07 ; H01L27/10 ; G06F17/50

Abstract:
A current mirror circuit includes a first current mirror leg and a second current mirror leg. The first current mirror leg is configured with N stages of first transistors coupled in series and with their respective gates tied together. The second current mirror leg is configured with N stages of second transistors coupled in series and with their respective gates tied together. The first transistors and the second transistors are implemented within a transistor array, the first transistors and the second transistors are coupled between a first reference terminal and a second reference terminal, the first transistors and the second transistors at 1st to Kth stages adjacent to the first reference terminal are implemented at corner regions of the transistor array, N and K are positive integers and K
Public/Granted literature
- US20160266597A1 Integrated Circuit With Transistor Array And Layout Method Thereof Public/Granted day:2016-09-15
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