Invention Grant
- Patent Title: Methods for improving wafer planarity and bonded wafer assemblies made from the methods
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Application No.: US15379759Application Date: 2016-12-15
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Publication No.: US09978582B2Publication Date: 2018-05-22
- Inventor: Gregory Batinica , Kameshwar Yadavalli , Qian Fan , Benjamin A. Haskell , Hussein S. El-Ghoroury
- Applicant: Ostendo Technologies, Inc.
- Applicant Address: US CA Carlsbad
- Assignee: Ostendo Technologies, Inc.
- Current Assignee: Ostendo Technologies, Inc.
- Current Assignee Address: US CA Carlsbad
- Agency: Womble Bond Dickinson (US) LLP
- Main IPC: H01L21/302
- IPC: H01L21/302 ; H01L21/02 ; H01L21/66 ; H01L23/31 ; H01L23/00 ; H01L29/20 ; H01L29/30

Abstract:
A method to improve the planarity of a semiconductor wafer and an assembly made from the method. In a preferred embodiment of the method, a compressive PECVD oxide layer such as SiO2 having a predetermined thickness or pattern is deposited on the second surface of a semiconductor wafer having an undesirable warp or bow. The thickness or pattern of the deposited oxide layer is determined by the measured warp or bow of the semiconductor wafer. The compressive oxide layer induces an offsetting compressive force on the second surface of the semiconductor wafer to reduce the warp and bow across the major surface of the semiconductor wafer.
Public/Granted literature
- US20170178891A1 Methods for Improving Wafer Planarity and Bonded Wafer Assemblies Made from the Methods Public/Granted day:2017-06-22
Information query
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