- Patent Title: Method for estimating depth of latent scratches in SiC substrates
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Application No.: US15300653Application Date: 2015-03-10
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Publication No.: US09991175B2Publication Date: 2018-06-05
- Inventor: Satoshi Torimi , Norihito Yabuki , Satoru Nogami
- Applicant: Toyo Tanso Co., Ltd.
- Applicant Address: JP Osaka-shi
- Assignee: TOYO TANSO CO., LTD.
- Current Assignee: TOYO TANSO CO., LTD.
- Current Assignee Address: JP Osaka-shi
- Agency: Westerman, Hattori, Daniels & Adrian, LLP
- Priority: JP2014-074748 20140331
- International Application: PCT/JP2015/001301 WO 20150310
- International Announcement: WO2015/151411 WO 20151008
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/66 ; H01L21/02 ; H01L21/04 ; H01L29/16

Abstract:
This method for estimating the depth of latent scratches in SiC substrates includes an etching step, a measurement step, and an estimation step. In the etching step, a SiC substrate in which at least the surface is formed from single crystal SiC, and which has been subjected to machining, is subjected to heat treatment under Si atmosphere to etch the surface of the SiC substrate. In the measurement step, the surface roughness or the residual stress of the SiC substrate which has been subjected to the etching step is measured. In the estimation step, the depth of latent scratches or the presence or absence of latent scratches in the SiC substrate before the etching step are estimated on the basis of the results obtained in the measurement step.
Public/Granted literature
- US20170110378A1 METHOD FOR ESTIMATING DEPTH OF LATENT SCRATCHES IN SiC SUBSTRATES Public/Granted day:2017-04-20
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