再颁专利
USRE39529E1 Graphic processing apparatus utilizing improved data transfer to reduce memory size
有权
利用改进的数据传输来减少存储器大小的图形处理装置
- 专利标题： Graphic processing apparatus utilizing improved data transfer to reduce memory size
- 专利标题（中）： 利用改进的数据传输来减少存储器大小的图形处理装置
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申请号： US09536646申请日： 2000-03-28
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公开(公告)号： USRE39529E1公开(公告)日： 2007-03-27
- 发明人: Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
- 申请人： Koyo Katsura , Shinichi Kojima , Noriyuki Kurakami
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Mattingly, Stanger, Malur & Brundidge, P.C.
- 优先权： JP63-93448 19880418
- 主分类号： G09G5/39
- IPC分类号： G09G5/39
摘要：
A Memory Interface and Video Attribute Controller (MIVAC) is inserted between a dynamic RAM (DRAM) capable of a consecutive data read operation, such as the operation associated with the static column mode, page mode, or nibble mode, and a graphic processor to provide a parallel data processing. A serial data transfer is executed on each data bus between the MIVAC and the DRAM, whereas parallel data transfer is conducted between the MIVAC and the graphic processor. As a result, the graphic processor can be configured with a reduced number of DRAMs so that the graphic processor operates without paying attention to the consecutive data read mode of the DRAM.