再颁专利
USRE39579E1 Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system
有权
半导体集成电路器件包括具有集成到单个芯片中的命令解码系统和逻辑电路的RAM以及具有命令解码系统的RAM的测试方法
- 专利标题： Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system
- 专利标题（中）： 半导体集成电路器件包括具有集成到单个芯片中的命令解码系统和逻辑电路的RAM以及具有命令解码系统的RAM的测试方法
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申请号： US09871978申请日： 2001-06-04
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公开(公告)号： USRE39579E1公开(公告)日： 2007-04-17
- 发明人: Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
- 申请人： Makoto Hatakenaka , Akira Yamazaki , Shigeki Tomishima , Tadato Yamagata
- 申请人地址： JP Tokyo
- 专利权人： Renesas Technology Corp.
- 当前专利权人： Renesas Technology Corp.
- 当前专利权人地址： JP Tokyo
- 代理机构： Leydig, Voit & Mayer, Ltd.
- 优先权： JP9-086600 19970404
- 主分类号： G06F11/00
- IPC分类号： G06F11/00
摘要：
A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector and are provided to the core unit of the synchronous dynamic random access memory for testing.
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