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    Multi-bank semiconductor memory device suitable for integration with logic
    1.
    发明授权
    Multi-bank semiconductor memory device suitable for integration with logic 失效
    适合与逻辑集成的多存储半导体存储器件

    公开(公告)号：US06310815B1

    公开(公告)日：2001-10-30

    申请号：US09131346

    申请日：1998-08-07

    申请人： Tadato Yamagata ,  Akira Yamazaki ,  Shigeki Tomishima ,  Yoshio Yukinari ,  Makoto Hatakenaka ,  Atsushi Miyanishi

    发明人： Tadato Yamagata ,  Akira Yamazaki ,  Shigeki Tomishima ,  Yoshio Yukinari ,  Makoto Hatakenaka ,  Atsushi Miyanishi

    IPC分类号： G11C800

    CPC分类号： G11C5/14 ,  G11C8/12

    摘要： Subbanks are arranged in four regions of a DRAM macro having a rectangular shape, bank control circuits are arranged in a prescribed region between these subbanks, and internal read/write data buses are arranged in a region different from the region where the bank control circuits are arranged. Since there is no crossing of the bank control circuits and the internal read/write data buses, the bank control circuits can be efficiently arranged to reduce the layout area. Accordingly, a semiconductor integrated circuit device including multi-bank memories which operates stably at high speed can be provided without increase of an area occupied by a chip.

    摘要翻译： 子行排列在具有矩形形状的DRAM宏的四个区域中，组控制电路布置在这些子行之间的规定区域中，并且内部读/写数据总线布置在与存储体控制电路的区域不同的区域中 安排。 由于银行控制电路和内部读/写数据总线没有交叉，因此可以有效地布置存储体控制电路以减少布局面积。 因此，可以在不增加芯片占有面积的情况下提供包括以高速稳定运行的多存储体存储器的半导体集成电路器件。

    Semiconductor integrated circuit device with large internal bus width, including memory and logic circuit
    2.
    发明授权
    Semiconductor integrated circuit device with large internal bus width, including memory and logic circuit 有权
    具有内部总线宽度大的半导体集成电路器件，包括存储器和逻辑电路

    公开(公告)号：US06163493A

    公开(公告)日：2000-12-19

    申请号：US208492

    申请日：1998-12-10

    申请人： Tadato Yamagata ,  Makoto Hatakenaka ,  Shigeki Tomishima ,  Akira Yamazaki

    发明人： Tadato Yamagata ,  Makoto Hatakenaka ,  Shigeki Tomishima ,  Akira Yamazaki

    IPC分类号： G11C11/407 ,  G11C5/14 ,  G11C11/4074 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

    CPC分类号： G11C11/4074 ,  G11C5/147

    摘要： A first internal power supply circuit receiving an external power supply voltage for generating a first internal power supply voltage and a second internal power supply circuit receiving the external power supply voltage for generating a second internal power supply voltage are provided within a DRAM. A sense amplifier operates by the first internal power supply voltage. A write driver and a GIO line precharge circuit operate by the second internal power supply voltage. A peripheral circuit operates by the external power supply voltage. As a result, the sense amplifier and the peripheral circuit will not be affected by the operation of the write driver and the GIO line precharge circuit.

    摘要翻译： 接收用于产生第一内部电源电压的外部电源电压的第一内部电源电路和接收用于产生第二内部电源电压的外部电源电压的第二内部电源电路设置在DRAM内。 读出放大器通过第一内部电源电压进行工作。 写驱动器和GIO线预充电电路由第二内部电源电压工作。 外围电路由外部电源供电。 结果，读出放大器和外围电路不会受到写入驱动器和GIO线路预充电电路的操作的影响。

    Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system
    3.
    再颁专利
    Semiconductor integrated circuit device comprising RAM with command decode system and logic circuit integrated into a single chip and testing method of the RAM with command decode system 有权
    半导体集成电路器件包括具有集成到单个芯片中的命令解码系统和逻辑电路的RAM以及具有命令解码系统的RAM的测试方法

    公开(公告)号：USRE39579E1

    公开(公告)日：2007-04-17

    申请号：US09871978

    申请日：2001-06-04

    申请人： Makoto Hatakenaka ,  Akira Yamazaki ,  Shigeki Tomishima ,  Tadato Yamagata

    发明人： Makoto Hatakenaka ,  Akira Yamazaki ,  Shigeki Tomishima ,  Tadato Yamagata

    IPC分类号： G06F11/00

    CPC分类号： G06F11/00

    摘要： A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector and are provided to the core unit of the synchronous dynamic random access memory for testing.

    摘要翻译： 半导体集成电路器件包括集成在单个半导体芯片上的逻辑电路和包括核心单元的同步动态随机存取存储器。 半导体集成电路装置包括：同步动态随机存取存储器控制电路，其从逻辑电路接收用于同步动态随机存取存储器的外部控制信号，并将内部控制信号输出到同步动态随机存取存储器的核心单元。 对于半导体集成电路器件的测试，通过外部端子提供外部测试信号。 外部测试信号由选择器选择，并提供给同步动态随机存取存储器的核心单元进行测试。

    Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core
    4.
    发明授权
    Semiconductor integrated circuit device comprising synchronous DRAM core and logic circuit integrated into a single chip and method of testing the synchronous DRAM core 失效
    半导体集成电路器件包括同步DRAM核心和逻辑电路集成到单个芯片中以及测试同步DRAM内核的方法

    公开(公告)号：US5910181A

    公开(公告)日：1999-06-08

    申请号：US964236

    申请日：1997-11-04

    申请人： Makoto Hatakenaka ,  Akira Yamazaki ,  Shigeki Tomishima ,  Tadato Yamagata

    发明人： Makoto Hatakenaka ,  Akira Yamazaki ,  Shigeki Tomishima ,  Tadato Yamagata

    IPC分类号： G11C11/407 ,  G11C11/401 ,  G11C29/02 ,  G11C29/14 ,  G11C29/16 ,  G11C29/48 ,  G06F11/00

    CPC分类号： G11C29/16 ,  G11C29/48

    摘要： A semiconductor integrated circuit device includes a logic circuit and a synchronous dynamic random access memory including a core unit, integrated on a single semiconductor chip. The semiconductor integrated circuit device includes a synchronous dynamic random access memory control circuit which receives external control signals for the synchronous dynamic random access memory from the logic circuit, and outputs internal control signals to the core unit of the synchronous dynamic random access memory. For testing of semiconductor integrated circuit device, external test signals are provided through external terminals. The external test signals are selected by a selector, and are provided to the core unit of the synchronous dynamic random access memory for testing.

    摘要翻译： 半导体集成电路器件包括集成在单个半导体芯片上的逻辑电路和包括核心单元的同步动态随机存取存储器。 半导体集成电路装置包括：同步动态随机存取存储器控制电路，其从逻辑电路接收用于同步动态随机存取存储器的外部控制信号，并将内部控制信号输出到同步动态随机存取存储器的核心单元。 对于半导体集成电路器件的测试，通过外部端子提供外部测试信号。 外部测试信号由选择器选择，并提供给同步动态随机存取存储器的核心单元进行测试。

    Synchronized clock generating apparatus
    8.
    发明授权
    Synchronized clock generating apparatus 失效
    同步时钟发生装置

    公开(公告)号：US5491438A

    公开(公告)日：1996-02-13

    申请号：US289837

    申请日：1994-08-12

    申请人： Yukio Miyazaki ,  Takenori Okitaka ,  Makoto Hatakenaka ,  Junji Mano

    发明人： Yukio Miyazaki ,  Takenori Okitaka ,  Makoto Hatakenaka ,  Junji Mano

    IPC分类号： G06F1/10 ,  H03K5/00 ,  H03K5/13 ,  H04L7/033 ,  H03L7/00

    CPC分类号： H04L7/0338 ,  G06F1/10 ,  H03K5/133 ,  H03K2005/00234

    摘要： A synchronized clock generating apparatus includes a delayed clock generating circuit including a plurality of serially connected delaying elements for generating delayed clock signals delayed successively relative to an incoming basic clock signal. Storage means includes a plurality of storage elements storing therein a predetermined level in response to transitions occurring in associated ones of said basic and delayed clock signals after a trigger signal which is asynchronous with the basic clock signal is applied thereto. A clock selection logic circuit is controlled by the output signal of the storage means for detecting the clock signal transition occurring closest in time to the application of the asynchronous trigger signal, and for selecting a desired one of said clock signals, based on the result of the detection, as a synchronized clock signal output.

    摘要翻译： 同步时钟发生装置包括延迟时钟产生电路，其包括多个串行连接的延迟元件，用于产生相对于输入的基本时钟信号连续延迟的延迟时钟信号。 存储装置包括多个存储元件，其中，在施加与基本时钟信号异步的触发信号之后，响应于在相关联的所述基本和延迟的时钟信号中发生的转换，存储其中的预定电平。 时钟选择逻辑电路由存储装置的输出信号控制，用于检测在施加异步触发信号时在时间上最近发生的时钟信号转换，并且基于所述时钟信号的结果来选择期望的一个时钟信号 检测，作为同步时钟信号输出。