Invention Application
WO0115171A3 FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT
审中-公开
使用三层金属互连的闪存存储器架构
- Patent Title: FLASH MEMORY ARCHITECTURE EMPLOYING THREE LAYER METAL INTERCONNECT
- Patent Title (中): 使用三层金属互连的闪存存储器架构
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Application No.: PCT/US0019303Application Date: 2000-07-14
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Publication No.: WO0115171A3Publication Date: 2002-09-12
- Inventor: BILL COLIN S , SU JOHATHAN SHI-CHANG , GUTALA RAVI P
- Applicant: ADVANCED MICRO DEVICES INC
- Assignee: ADVANCED MICRO DEVICES INC
- Current Assignee: ADVANCED MICRO DEVICES INC
- Priority: US37947999 1999-08-23
- Main IPC: G11C16/06
- IPC: G11C16/06 ; G11C8/10 ; G11C8/12 ; H01L21/8247 ; H01L27/10 ; H01L27/115 ; H01L29/788 ; H01L29/792 ; G11C8/00 ; G11C16/08
Abstract:
The present invention discloses a memory wordline decoder that includes plurality of pre-decoded address lines that are electrically connected with a global x-decoder. A sub x-decoder is electrically connected with the global x-decoder for receiving electrical control signals from the global x-decoder. A memory sector is electrically connected with the sub x-decoder. The global x-decoder selectively controls the sub x-decoder to select a plurality of wordlines in the memory sector. A vertical x-decoder is electrically connected with the global x-decoder and the sub x-decoder. The vertical x-decoder is used to select a predetermined wordline by the global x-decoder during operation.
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