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公开(公告)号：WO2023091459A1
公开(公告)日：2023-05-25
申请号：PCT/US2022/050061
申请日：2022-11-16
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： GOLDEN, Michael , BLINZER, Paul , TALISAYON, Magiting , MASANAM, Srikanth , BUTANI, Ripal , SWAMINATHAN, Upasanah
Abstract: Within a processing system, thread count asymmetries manifest when one or more cores of a processing device are disabled. To determine such thread count asymmetries, discovery operations are performed to determine thread count asymmetries for one or more hierarchy levels of a processing device based on a number of threads per enumerated instance within the hierarchy level. In response to the determining a thread count asymmetry, one thread identifier for each enumerated instance within the asymmetric hierarchy level is defined to determine a representation of the asymmetry. Using the representation of the symmetry, software tasks associated with one or more application within the processing system are performed.
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公开(公告)号：WO2023086205A1
公开(公告)日：2023-05-19
申请号：PCT/US2022/047922
申请日：2022-10-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： GANAPATHY, Shrikanth , ECKERT, Yasuko , GUTIERREZ, Anthony , SANGAIAH, Karthik Ramu , BHARADWAJ, Vedula Venkata Srikant
IPC: G06F9/50
Abstract: A processor includes a controller and plurality of chiplets, each chiplet including a plurality of processor cores. The controller provides chiplet-level performance information for the chiplets that identifies a performance of each chiplet at each of a plurality of performance levels for specified sets of processor cores on that chiplet. The controller receives an identification of one or more selected chiplets from among the plurality of chiplets for which a specified number of processor cores are to be configured at a given performance level, the one or more selected chiplets having been selected based on the chiplet-level performance information and performance requirements. The controller configures the specified number of processor cores of the one or more selected chiplets at the given performance level. A task is then run on the specified number of processor cores of the one or more selected chiplets at the given performance level.
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3.发明申请
公开(公告)号：WO2023086204A1
公开(公告)日：2023-05-19
申请号：PCT/US2022/047900
申请日：2022-10-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： CURTIS, Nicholas James
Abstract: Methods and systems for runtime management by an accelerator-resident manager. Techniques include receiving, by the manager, a representation of a processing flow of an application, including a plurality of kernels and respective dependencies. The manager, then, assigns the plurality of kernels to one or more APUs managed it and launches the plurality of kernels on their assigned APUs to run in an iteration according to the respective dependencies.
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公开(公告)号：WO2023064728A1
公开(公告)日：2023-04-20
申请号：PCT/US2022/077848
申请日：2022-10-10
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： DONG, HaiKun , CHRISTIDIS, Kostantinos Danny , WANG, Ling-Ling , WU, MinHua , CONG, Gaojian , WANG, Rui
IPC: G06F11/00
Abstract: Systems, apparatuses, and methods for implementing duplicated registers for access by initiators across multiple semiconductor dies are disclosed. A system includes multiple initiators on multiple semiconductor dies of a chiplet processor. One of the semiconductor dies is the master die, and this master die has copies of registers which can be accessed by the multiple initiators on the multiple semiconductor dies. When a given initiator on a given secondary die generates a register access, the register access is routed to the master die and a particular duplicate copy of the register maintained for the given secondary die. From the point of view of software, the multiple semiconductor dies appear as a single die, and the multiple initiators appear as a single initiator. Multiple types of registers can be maintained by the master die, with a flush register being one of the register types.
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公开(公告)号：WO2023018783A1
公开(公告)日：2023-02-16
申请号：PCT/US2022/039934
申请日：2022-08-10
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： MANGASER, Ramon , GOPALAKRISHNAN, Karthik , CHU, Andy Huei , JAYARAMAN, Pradeep
Abstract: A data transmission system includes a first circuit, a second circuit, and a reference voltage generation circuit. The first circuit includes a transmitter powered by a first power supply voltage and having an input for receiving a data output signal, and an output. The second circuit includes a receiver powered by a second power supply voltage and having a first input coupled to the output of the transmitter, a second input for receiving a reference voltage, and an output for providing a data input signal. The reference voltage generation circuit forms the reference voltage by mixing a first signal generated by the first circuit based on the first power supply voltage and a second signal generated by the second circuit based on the second power supply voltage.
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Patent Agency Ranking
公开(公告)号：WO2023014512A1
公开(公告)日：2023-02-09
申请号：PCT/US2022/037897
申请日：2022-07-21
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： VENKATRAMANI, Rajagopalan , GADDI, Renato Dimatula , MARTINEZ, Liane , SANTOS, Warren Alexander , SURELL, Dennis Glenn Lozanta
IPC: G06F30/392 , G06F30/394 , G06F30/398 , G06F115/12 , G06F113/18
Abstract: A system and method for automatically generating placement of vias within redistribution layers of a semiconductor package are described. A user defines attributes to use for automatic via generation in redistribution layers of a semiconductor package (702). The circuitry of a processor of a computing device used by the user executes instructions of an automatic redistribution layer (RDL) via generator (704). The automatic via generator uses the attributes, data indicative of the RDL netlist of signal routes within the RDL, and RDL mask layout data representing the signal masks of the metal layers within the RDL. The processor generates placement of vias for in the RDL based on the attributes and an identification of overlapping regions between metal layers.
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公开(公告)号：WO2023009468A1
公开(公告)日：2023-02-02
申请号：PCT/US2022/038246
申请日：2022-07-25
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ESTLICK, Michael , SWANSON, Erik , DIXON, Eric , BAUMGARTNER, Todd
Abstract: In some implementations, a processor includes a plurality of parallel instruction pipes, a register file includes at least one shared read port configured to be shared across multiple pipes of the plurality of parallel instruction pipes. Control logic controls multiple parallel instruction pipes to read from the at least one shared read port. In certain examples, the at least one shared register file read port is coupled as a single read port for one of the parallel instruction pipes and as a shared register file read port for a plurality of other parallel instruction pipes.
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公开(公告)号：WO2023004028A1
公开(公告)日：2023-01-26
申请号：PCT/US2022/037848
申请日：2022-07-21
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ACHARYA, Anirudh , GODEY, Sreekanth , WU, Ruijin
IPC: G06F9/50 , G06F9/455 , G06F9/5038 , G06F9/5044 , G06F9/505 , G06F9/5077
Abstract: A processing unit [100] is configured differently based on an identified workload [200, 225], and each configuration of the processing unit is exposed to software (e.g., to a device driver [103]) as a different virtual processing unit [111. 112]. Using these techniques, a processing system is able to provide different configurations of the processing unit to support different types of workloads, thereby conserving system resources. Further, by exposing the different configurations as different virtual processing units, the processing system is able to use existing device drivers or other system infrastructure to implement the different processing unit configurations.
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公开(公告)号：WO2023278338A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/035142
申请日：2022-06-27
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： ALSOP, Johnathan , DUTU, Alexandru , AGA, Shaizeen , JAYASENA, Nuwan
IPC: G06F12/02 , G06F12/0855 , G06F12/0879 , G06F15/78 , G06F12/0888 , G06F12/0811 , G06F12/0238 , G06F12/0284 , G06F12/084 , G06F12/0846 , G06F12/0857 , G06F12/0871 , G06F2212/1024 , G06F2212/502
Abstract: Dynamically coalescing atomic memory operations for memory-local computing is disclosed. In an embodiment, it is determined whether a first atomic memory access and a second atomic memory access are candidates for coalescing. In response to a triggering event, the atomic memory accesses that are candidates for coalescing are coalesced in a cache prior to requesting memory-local processing by a memory-local compute unit. The atomic memory accesses may be coalesced in the same cache line or atomic memory accesses in different cache lines may be coalesced using a multicast memory-local processing command.
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10.发明申请
公开(公告)号：WO2023278193A1
公开(公告)日：2023-01-05
申请号：PCT/US2022/034192
申请日：2022-06-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： MEHRA, Amitabh , AHRENS, Jerry A. , HARWANI, Anil , BORN, Richard Martin , ROBINSON, Dirk J. , ALVERSON, William R. , KNIGHT, Joshua Taylor
IPC: G06F1/08 , G06F1/28 , H03K5/00006
Abstract: Methods and apparatuses control the clock rate of a processing unit. The methods and apparatus control the clock rate by generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking. The methods include: receiving an analog voltage supply in response to detecting overclocking in the processing unit; dynamically sensing measurements of an output voltage from a voltage generator based on the received analog voltage supply; determining characteristics of a voltage droop in the output voltage based on the dynamically sensed output voltage measurements; determining a frequency adjustment for the clock rate of the processing unit based on the determined characteristics of the voltage droop; and generating an output clock rate based on the determined frequency adjustment such that the processing unit maintains the overclocking.
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