The invention relates to a delay circuit having adjustable delay. The delay circuit comprises a first block (1) and a second block (2) that is connected in outgoing circuit thereto. Said blocks each have a chain of delay elements (11 to 16, 21 to 26). A switch group (4, 5) is assigned to each block and enables output-side taps on the delay elements (11 to 16, 21 to 26) to be selected by means of switches (S1 to S6) in order to be able to select a desired delay time. In order to simultaneously control the switch (S6), which is connected to the output-side delay element (16) of the first block (1), and the switch (S6), which is connected to the input-side delay element (26) of the second block (2), the control inputs of these switches are connected to one another. This prevents the occurrence of disturbing pulses also in the event of high clock-pulse rates of clock signals (A) that can be applied to the delay elements on the input side. For this reason, the inventive delay circuit is suited especially for use in delay closed loops in DDR memory chips.