公开(公告)号：WO2021191238A1

公开(公告)日：2021-09-30

申请号：PCT/EP2021/057492

申请日：2021-03-23

Applicant: ABB POWER GRIDS SWITZERLAND AG

Inventor： TRAINOR, John J. ,  TAYLOR, Russell John

IPC: G06F13/38 ,  G06F1/266 ,  G06F1/325 ,  G06F13/385 ,  G06F13/4022 ,  G06F13/4068 ,  H03K5/133

Abstract: An apparatus includes a connector port configured to be selectably connected with and disconnected from a peripheral device. A detector is configured to provide an output indicating the connection of the peripheral device with the connector port with a time delay between connection of the peripheral device with the connector port and outputting the signal. A data switch is operatively coupled with the detector and a communication pin of the connector port and to selectably enable and disable data communication between the communication pin and a computer board in response to the output of the detector. A power switch is operatively coupled with the detector, the power supply pin, and a DC power supply and is configured to selectably connect and disconnect the power supply and the power supply pin in response to the output of the detector.

公开(公告)号：WO2021145970A1

公开(公告)日：2021-07-22

申请号：PCT/US2020/063394

申请日：2020-12-04

Applicant: QUALCOMM INCORPORATED

Inventor： CHAKKIRALA, Subbarao Surendra ,  GALAL, Sherif

IPC: H03K5/133 ,  G06F1/04 ,  G06F1/08 ,  H03F3/217 ,  H03K19/20 ,  H03K2005/00078 ,  H03K2005/00234 ,  H03K3/037 ,  H03K5/00 ,  H03K5/135

Abstract: In certain aspects, a delay circuit includes a multiplexer, a first delay path coupled between an input of the delay circuit and a first input of the multiplexer, and a second delay path coupled between the input of the delay circuit and a second input of the multiplexer. The first delay path includes a first delay device, and the second delay path includes a first inverter, a second delay device, and a second inverter. In other aspects, a delay circuit includes a latch including a first input, a second input, and an output. The first input of the latch is coupled to an input of the delay circuit. The delay circuit also includes a delay path coupled between the input of the delay circuit and the second input of the latch, wherein the delay path includes a pulse generator and a delay device.

公开(公告)号：WO02052725A2

公开(公告)日：2002-07-04

申请号：PCT/DE2001/004311

申请日：2001-11-15

IPC: H03K5/13 ,  H03K5/131 ,  H03K5/133 ,  H03K5/00

CPC classification number: H03K5/131 ,  H03K5/133

Abstract: The invention relates to a delay circuit having adjustable delay. The delay circuit comprises a first block (1) and a second block (2) that is connected in outgoing circuit thereto. Said blocks each have a chain of delay elements (11 to 16, 21 to 26). A switch group (4, 5) is assigned to each block and enables output-side taps on the delay elements (11 to 16, 21 to 26) to be selected by means of switches (S1 to S6) in order to be able to select a desired delay time. In order to simultaneously control the switch (S6), which is connected to the output-side delay element (16) of the first block (1), and the switch (S6), which is connected to the input-side delay element (26) of the second block (2), the control inputs of these switches are connected to one another. This prevents the occurrence of disturbing pulses also in the event of high clock-pulse rates of clock signals (A) that can be applied to the delay elements on the input side. For this reason, the inventive delay circuit is suited especially for use in delay closed loops in DDR memory chips.

Abstract translation: 有与由第一块（1）和一个第二nachgestalteten块（2），每一个具有的延迟歌曲链（11至16，21至26）表明可调延迟的延迟电路。 每个块具有与由开关装置（S1到S6）的延迟元件，其输出侧的抽头（11〜16，21〜26）相关联的开关组（4，5）是可选择的，以能够选择期望的延迟时间。 对于第一个块（1）连接的开关（S6）和第二块的输入侧的延迟元件（26）的输出侧的延迟元件（16）的同时致动（2）连接的开关（S6）是其控制输入端连接在一起。 以这种方式，甚至可以在输入侧的高时钟速率可以被放置抵靠延迟元件的时钟信号（A）来避免故障。 因此所描述的延迟电路特别适合用于在DDR存储器芯片延迟锁定环路中使用。

公开(公告)号：WO2022115849A2

公开(公告)日：2022-06-02

申请号：PCT/US2021/072568

申请日：2021-11-23

Applicant: MICROCHIP TECHNOLOGY INCORPORATED

Inventor： SONI, Ravish

IPC: H04L25/03 ,  H03K17/6871 ,  H03K5/133 ,  H04L2025/03445 ,  H04L25/03057 ,  H04L25/03146

Abstract: Decision feedback equalization (DFE) taps and related apparatuses and methods are disclosed. An apparatus includes a first electrically controllable switch, a second electrically controllable switch, and one or more delay elements. The first electrically controllable switch receives a history bit and selectively provides the history bit to gate terminals of first transistors of a DFE tap circuitry. The second electrically controllable switch receives a complementary history bit and selectively provides the complementary history bit to second gate terminals of second transistors of the DFE tap circuitry. The one or more delay elements provide one or more delayed data integration clock signals responsive to one or more data integration clock signals. A complementary delayed data integration clock signal controls switching of the first electrically controllable switch and the second electrically controllable switch.

公开(公告)号：WO2018232002A1

公开(公告)日：2018-12-20

申请号：PCT/US2018/037356

申请日：2018-06-13

Applicant: MICRON TECHNOLOGY, INC

Inventor： MA, Yantao

IPC: H03K5/133 ,  H03L7/08

Abstract: Various embodiments include apparatus and methods that have a multiple phase generator. The multiple phase generator can include multiple delay devices coupled with a set of phase mixers having a specified mixing ratio to generate signals separated in phase by a constructed amount of phase based on the specified mixing ratio. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：WO00067381A1

公开(公告)日：2000-11-09

申请号：PCT/CA2000/000468

申请日：2000-05-01

IPC: G11C11/407 ,  G06F1/08 ,  H03K5/00 ,  H03K5/133 ,  H03K5/15 ,  H03L7/07 ,  H03L7/08 ,  H03L7/081 ,  H03L7/16

CPC classification number: H03L7/06 ,  H03K5/00006 ,  H03K5/15046 ,  H03L7/07 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/089 ,  H03L7/16

Abstract: A frequency multiplier circuit (100) comprising a delay line receiving at one end thereof a reference clock (102) for generating clock tap outputs from respective ones of a plurality of period matched delay elements (101); a clock combining circuit (TOG) responsive to pairs of tap outputs for generating a rising and falling edge of an output clock pulse from respective ones of the pairs whereby the output clock period is less than the input clock period. The delay line may be included in a delay-locked loop to match the period of the delay elements (101). A plurality of combining circuits cells (TOG) are provided, each cell having inputs respectively coupled to ones of a predetermined number of delay stage tap outputs, each cell providing complementary outputs. A selector (106) is responsive to a selection control signal from a phase detector (112) for selecting an output from one of a pair of complementary outputs of one of the combining cells.

Abstract translation: 一种倍增器电路（100），包括延迟线，其一端接收用于从多个周期匹配延迟元件（101）中的相应延迟元件产生时钟抽头输出的参考时钟（102）。 响应于抽头对输出的时钟组合电路（TOG），用于从输出时钟周期小于输入时钟周期产生输出时钟脉冲的上升沿和下降沿。 延迟线可以包括在延迟锁定环路中以匹配延迟元件（101）的周期。 提供多个组合电路单元（TOG），每个单元具有分别耦合到预定数量的延迟级抽头输出中的一个的输入，每个单元提供互补输出。 选择器（106）响应于来自相位检测器（112）的选择控制信号，用于从组合单元之一的一对互补输出之一中选择一个输出。

公开(公告)号：WO00049712A1

公开(公告)日：2000-08-24

申请号：PCT/DE2000/000464

申请日：2000-02-18

IPC: H03K5/00 ,  H03K5/04 ,  H03K5/13 ,  H03K5/133 ,  H03K5/15

CPC classification number: H03K5/04 ,  H03K5/133 ,  H03K2005/0013

Abstract: The invention relates to a delay circuit for electrical signals, comprising at least one delay element which sends a time-delayed input signal to an electrical circuit, wherein the delay element is connected to a stabilized constant voltage that is independent from the supply voltage of the electrical circuit.

Abstract translation: 本发明提供了用于与至少一个延迟元件，其输出延迟在时间上的电路，其中所述延迟元件连接到一个稳定的恒定电压，这是独立于电路的电源电压的输入信号的电信号的延迟电路。

公开(公告)号：WO2021092601A2

公开(公告)日：2021-05-14

申请号：PCT/US2020/067195

申请日：2020-12-28

Applicant: FUTUREWEI TECHNOLOGIES, INC.

Inventor： MCHUGH, Timothy ,  IEHL, Brian ,  CONNELL, Larry

IPC: H03K5/133 ,  H03K5/156 ,  H03K5/1565

Abstract: A frequency doubler circuit is presented that provides a way to quickly and simply calibrate the phase delay required for a differential 50% output duty cycle frequency doubler in a manner that is low in cost and current drain. A fully differential approach is used, in which the components of a differential input signal (clkjn, clkjnb) are used to generate a differential output signal (clk_out, clk_outb) and a delayed differential output signal (clk_dly_out, clk_dly_outb). The differential output signal and the delayed differential output signal are combined in the logic circuitry (551, 553) to determine the components of the differential double frequency output signal (2x_clk, 2x_clkb). Outputs of the logic circuitry are used to adjust the amount of delay (541: control) in the delayed output signal so that the double frequency output signal has a duty cycle of 50%. In some embodiments, the positive and negative components of the delayed signal can be adjusted independently (541: control).

公开(公告)号：WO2019010088A1

公开(公告)日：2019-01-10

申请号：PCT/US2018/040349

申请日：2018-06-29

Applicant: INTEL CORPORATION

Inventor： LI, William ,  NASROULLAHI, Mohsen ,  NGUYEN, Khoa

IPC: H03L7/081 ,  H03K5/133 ,  H03L7/095

Abstract: An apparatus is provided to improve lock time of a phase locked loop, wherein the apparatus comprises: a ring oscillator including at least two delay stages, wherein each delay stage has a controllable delay; and a multiphase frequency monitor coupled to the ring oscillator to monitor frequency at an output of at least two delay stages of the ring oscillator.

公开(公告)号：WO2018230338A1

公开(公告)日：2018-12-20

申请号：PCT/JP2018/020651

申请日：2018-05-30

Applicant: ソニーセミコンダクタソリューションズ株式会社

Inventor： 田畑　満志

IPC: H03K5/00 ,  H03K5/1252 ,  H03K5/133

Abstract: 本技術は、出力クロックにおけるヒゲの発生を防止することができるようにするクロックイネーブラ回路に関する。 ゲート信号生成部は、入力クロックとイネーブル信号とに基づいて、入力クロックを有効にするゲート信号を生成し、クロック信号出力部は、ゲート信号のレベルに応じて入力クロックを有効にすることで、出力クロックを出力する。ゲート信号生成部は、イネーブル信号のレベル変化のタイミングを、クロック信号出力部において入力クロックが有効にならないタイミングまで遅延させることで、ゲート信号を生成する。本技術は、クロックイネーブラ回路に適用することができる。