An arithmetic unit comprising a plurality of adder blocks (200, 202, 204, 206, 208, 210, 212), whereby each adder block consists of a plurality of individual adders, a carry-look-ahead element (214), a carry-look-ahead element (216) and a carry-look-ahead element run-through output (218). A signal at the carry-look-ahead element run-through output (218) of an adder block can indicate that a carry-look-ahead element is running through an adder block. A clock-pulse generator for supplying the adder blocks with operands to be processed is slowed according to the carry-look-ahead element run-through output signal of an adder block. In order to handle a variable of the lowest value bit, a device (224) is provided for determining in which adder block (206) of said adder blocks a lowest value bit of an operand to be subtracted is located. A device (222) is also provided in order to deactivate a carry-look-ahead element run-through output of one or several adder blocks which are provided for low value positions in relation to the adder block in which the lowest value bit of the operand that is to be substituted is located. Finally, a device (230) is provided for feeding a carry-look-ahead element (C_ein) into the carry-look-ahead element input of the adder block in which the lowest value bit of the operand that is to be substituted is located, thereby ensuring that bits below the lowest value bits of the operand lead neither to artificial panic signals or falsify a subtraction result.