Invention Application
- Patent Title: INTEGRATED CIRCUIT PACKAGE CONFIGURATION INCORPORATING SHIELDED CIRCUIT ELEMENT
- Patent Title (中): 集成电路封装配置保护电路元件
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Application No.: PCT/US0332649Application Date: 2003-10-15
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Publication No.: WO2004036654A3Publication Date: 2004-07-01
- Inventor: WEI DERRICK C , SHI YING , SMITH KEVIN G , PROFFITT STEVEN P , THOMSEN AXEL , PIETRUSZYNSKI DAVID M , ZHANG LIGANG
- Applicant: SILICON LAB INC
- Assignee: SILICON LAB INC
- Current Assignee: SILICON LAB INC
- Priority: US41854602 2002-10-15; US46396103 2003-06-18
- Main IPC: H01L23/552
- IPC: H01L23/552 ; H01L23/64 ; H01L23/498 ; H01L23/522
Abstract:
An electromagnetically-shielded high-Q inductor may be fabricated within a multi-layer package substrate (MLS). The inductor is preferably constructed as a loop structure on a layer of the MLS, and a shielding structure is formedaround the inductor to substantially enclose the inductor in a Faraday cage-like enclosure. The shielding structure includes a top plate formed above the inductor on another layer of the MLS, and a bottom plate formed on yet another layer of the MLS or on a layer of an integrated circuit die which is below and attached to the MLS, preferably using solder bumps. Shielding structure sidewalls may be formed by a ring of stacked vias or via channels. The inductor is preferably connected to stacked vias which provide a connection to the underlying integrated circuit die by way of additional solder bumps and cut-outs through the bottom plate of the shielding structure.
Information query
IPC分类: